H. Then, M. Radosavljevic, P. Agababov, I. Ban, R. Bristol, M. Chandhok, S. Chouksey, B. Holybee, C.Y. Huang, B. Krist, K. Jun, P. Koirala, K. Lin, T. Michaelos, R. Paul, J. Peck, W. Rachmady, D. Staines, T. Talukdar, N. Thomas, T. Tronic, P. Fischer, W. Hafez
{"title":"GaN and Si Transistors on 300mm Si(111) enabled by 3D Monolithic Heterogeneous Integration","authors":"H. Then, M. Radosavljevic, P. Agababov, I. Ban, R. Bristol, M. Chandhok, S. Chouksey, B. Holybee, C.Y. Huang, B. Krist, K. Jun, P. Koirala, K. Lin, T. Michaelos, R. Paul, J. Peck, W. Rachmady, D. Staines, T. Talukdar, N. Thomas, T. Tronic, P. Fischer, W. Hafez","doi":"10.1109/VLSITechnology18217.2020.9265093","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265093","url":null,"abstract":"We expand on our work in [1] by demonstrating both Si P- and NMOS finfet transistors monolithically integrated with GaN transistors on 300mm Si(111) wafers using 3D integration. With the Si finfet architecture, we are able to take advantage of the fin orientations of the transferred Si(100) crystal to fabricate both high performance Si P- and NMOS transistors. Furthermore, we demonstrate a variety of GaN transistor innovations, including enhancement (e-mode) and depletion mode (d-mode) GaN NMOS transistor with high $mathrm{I}_{mathrm{D}}=1.8mathrm{m}_{1}mathrm{W}mu mathrm{m};mathrm{GaN}$ Schottky gate transistor producing high saturated power of 20dBm with peak PAE=57% at 28GHz; high performing, low leakage cascode and multi-gate GaN transistors; and GaN Schottky diodes with ultra-low $mathrm{C}_{mathrm{OFF}}$ for ESD protection, all integrated on 300mm Si(111) wafer.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"44 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85832804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Chujo, K. Sakui, H. Ryoson, S. Sugatani, Tomoji Nakamura, T. Ohba
{"title":"Bumpless Build Cube (BBCube): High-Parallelism, High-Heat-Dissipation and Low-Power Stacked Memory Using Wafer-Level 3D Integration Process","authors":"N. Chujo, K. Sakui, H. Ryoson, S. Sugatani, Tomoji Nakamura, T. Ohba","doi":"10.1109/VLSITechnology18217.2020.9265038","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265038","url":null,"abstract":"The superior electrical performance of 3D integration (3DI) with bumpless wafer-on-wafer (WOW) was clarified by 3D electromagnetic (EM) field analysis. We propose a high parallelism stacked memory, named “BBCube”, using WOW. In comparison with conventional high-bandwidth memory (HBM), BBCube can achieve a bandwidth four-times higher, at 1.4 TB/s, with only 13 % of the I/O power consumption, at 0.29 W. Furthermore, it should have sufficient potential to realize 32-times higher bandwidth and four-times more stacking levels.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85679520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Bao, K. Watanabe, J. Zhang, H. Zhou, M. Sankarapandian, J. Li, S. Pancharatnam, P. Jamison, R. Southwick, M. Wang, J. Demarest, J. Guo, N. Loubet, V. Basker, D. Guo, V. Narayanan, B. Haran, H. Bu, M. Khare
{"title":"Selective Enablement of Dual Dipoles for Near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies","authors":"R. Bao, K. Watanabe, J. Zhang, H. Zhou, M. Sankarapandian, J. Li, S. Pancharatnam, P. Jamison, R. Southwick, M. Wang, J. Demarest, J. Guo, N. Loubet, V. Basker, D. Guo, V. Narayanan, B. Haran, H. Bu, M. Khare","doi":"10.1109/VLSITechnology18217.2020.9265010","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265010","url":null,"abstract":"We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82107435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Gupta, H. Mertens, Z. Tao, S. Demuynck, J. Bömmels, G. Arutchelvan, K. Devriendt, O. Pedreira, R. Ritzenthaler, S. Wang, D. Radisic, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, H. Zahedmanesh, S. Subramanian, F. Schleicher, T. Hopf, A. Peter, N. Rassoul, H. Debruyn, I. Demonie, Y. Siew, T. Chiarella, B. Briggs, D. Zhou, E. Rosseel, A. De Keersgieter, E. Capogreco, E. Litta, G. Boccardi, S. Baudot, G. Mannaert, N. Bontemps, A. Sepúlveda, S. Mertens, M. Kim, E. Dupuy, K. Vandersmissen, S. Paolillo, D. Yakimets, B. Chehab, P. Favia, C. Drijbooms, J. Cousserier, M. Jaysankar, F. Lazzarino, P. Morin, E. Sanchez, J. Mitard, C. Wilson, F. Holsteyns, Z. Tökei, N. Horiguchi
{"title":"Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node","authors":"A. Gupta, H. Mertens, Z. Tao, S. Demuynck, J. Bömmels, G. Arutchelvan, K. Devriendt, O. Pedreira, R. Ritzenthaler, S. Wang, D. Radisic, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, H. Zahedmanesh, S. Subramanian, F. Schleicher, T. Hopf, A. Peter, N. Rassoul, H. Debruyn, I. Demonie, Y. Siew, T. Chiarella, B. Briggs, D. Zhou, E. Rosseel, A. De Keersgieter, E. Capogreco, E. Litta, G. Boccardi, S. Baudot, G. Mannaert, N. Bontemps, A. Sepúlveda, S. Mertens, M. Kim, E. Dupuy, K. Vandersmissen, S. Paolillo, D. Yakimets, B. Chehab, P. Favia, C. Drijbooms, J. Cousserier, M. Jaysankar, F. Lazzarino, P. Morin, E. Sanchez, J. Mitard, C. Wilson, F. Holsteyns, Z. Tökei, N. Horiguchi","doi":"10.1109/VLSITechnology18217.2020.9265113","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265113","url":null,"abstract":"Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80744248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Toprasertpong, Z. Lin, T. Lee, M. Takenaka, S. Takagi
{"title":"Asymmetric Polarization Response of Electrons and Holes in Si FeFETs: Demonstration of Absolute Polarization Hysteresis Loop and Inversion Hole Density over $2times 10^{13}mathrm{cm}^{-2}$","authors":"K. Toprasertpong, Z. Lin, T. Lee, M. Takenaka, S. Takagi","doi":"10.1109/VLSITechnology18217.2020.9265015","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265015","url":null,"abstract":"We have investigated the device operation of Si ferroelectric FETs (FeFET) through direct measurements of polarization and electron/hole densities in p-FeFETs and n-FeFETs. Unlike electrons in n-FeFETs, inversion holes in p-FeFETs are found to be well coupled with ferroelectric polarization, resulting in inversion hole density $N_{s}$ enhanced up to $2.5times 10^{13}$ cm−2. Based on experimentally-confirmed ferroelectric-semiconductor coupling behaviors, we propose a method to extract absolute polarization in ferroelectric gate stacks without centering P-V loops. We demonstrate that obtaining accurate polarization states is a key to understand the FeFET characteristics: it explains the physical origin of a difference in the memory window between p- and n-FeFETs.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"15 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89833735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Tsai, T. Ku, M.F. Chen, W. Chiou, C. Wang, Douglas C. H. Yu
{"title":"Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)","authors":"C. Tsai, T. Ku, M.F. Chen, W. Chiou, C. Wang, Douglas C. H. Yu","doi":"10.1109/VLSITechnology18217.2020.9265044","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265044","url":null,"abstract":"A 12-high (12-Hi) die stack using low temperature SoIC bonding and stacking technology is presented and demonstrated for the application of HBM. The daisy chains in the 12-Hi structure incorporating over ten thousand TSVs and bonds are tested. Liner I-V curves are obtained to demonstrate the good bonding and stacking quality. The electrical link from a base logic die to top DRAM is built up to study the bandwidth and power consumption. Compared to $mu mathrm{bump}$ technology, the bandwidth for 12-Hi and 16-Hi structure using the SoIC technology shows the improvement of 18% and 20%, respectively and the power efficiency demonstrates the improvement of 8% and 15%, respectively. Also, the thermal performance for the 12-Hi and 16-Hi SoIC-bond structures are improved by 7% and 8%, respectively. Based on the proposed technologies, the scalability of bond pitch to sub-ten $mumathrm{m}$ and die thickness to be thinner is prospected.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90462832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Quality N+/P Junction of Ge Substrate Prepared by initiated CVD Doping Process","authors":"Jae Hwan Kim, S. Shin, T. Lee, W. Hwang, B. Cho","doi":"10.1109/VLSITechnology18217.2020.9265108","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265108","url":null,"abstract":"For the first time, a novel co-doping scheme of P and Sn into Ge substrate using an initiated CVD (iCVD) dopant-containing polymer film is successfully developed. This optimized doping process provides high carrier concentration n-type doping of 3 $times 10^{20}mathrm{cm}^{-3}$ with a shallow junction depth of 50 nm. The enhancement of the P carrier concentration is attributed to less point defect generation during dopant injection and the strain relief effect induced by Sn co-doping with P into the Ge substrate. The Ge nMOSFETs with co-iCVD doping at the source/drain regions show lower off-state leakage current, higher on-current values, and lower contact resistivity compared to the Ge nMOSFETs with conventional ion implantation.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82540226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Changfeng Yang, Chun-Yu Wu, Ming-Han Yang, Wayne Wang, Ming-Ta Yang, Ta-Chun Chien, Vincent Fan, Shih-Chi Tsai, Yung-Huei Lee, W. Chu, Arthur Hung
{"title":"Industrially Applicable Read Disturb Model and Performance on Mega-Bit 28nm Embedded RRAM","authors":"Changfeng Yang, Chun-Yu Wu, Ming-Han Yang, Wayne Wang, Ming-Ta Yang, Ta-Chun Chien, Vincent Fan, Shih-Chi Tsai, Yung-Huei Lee, W. Chu, Arthur Hung","doi":"10.1109/VLSITechnology18217.2020.9265060","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265060","url":null,"abstract":"The read disturb performance and industrially applicable model of mega-bit level embedded RRAM with standard 28 nm select transistor are demonstrated in this study. At first, 100k endurance test on 0.5 Mb RRAM 1 T1R array is implemented and non-degraded memory window with high read disturb immunity results are acquired. Contrary to conventional analysis on major bits, the read disturb model is especially investigated on tail bits in this work. Furthermore, the read disturb performance for chip user condition with nano-second level pulse width is well emulated by long pulse, which provides a time-efficient way to evaluate read disturb performance at product level. As a consequence, the mega-bit 28 nm RRAM array in this work is able to sustain larger than 1 E 18 read counts at a rigorous fail criteria.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"91 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74964936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Vandooren, Z. Wu, N. Parihar, J. Franco, B. Parvais, P. Matagne, H. Debruyn, G. Mannaert, K. Devriendt, L. Teugels, E. Vecchio, D. Radisic, E. Rosseel, A. Hikavyy, B. Chan, N. Waldron, J. Mitard, G. Besnard, A. Alvarez, G. Gaudin, W. Schwarzenbach, I. Radu, B. Nguyen, K. Huet, T. Tabata, F. Mazzamuto, S. Demuynck, J. Boemmels, N. Collaert, N. Horiguchi
{"title":"3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters","authors":"A. Vandooren, Z. Wu, N. Parihar, J. Franco, B. Parvais, P. Matagne, H. Debruyn, G. Mannaert, K. Devriendt, L. Teugels, E. Vecchio, D. Radisic, E. Rosseel, A. Hikavyy, B. Chan, N. Waldron, J. Mitard, G. Besnard, A. Alvarez, G. Gaudin, W. Schwarzenbach, I. Radu, B. Nguyen, K. Huet, T. Tabata, F. Mazzamuto, S. Demuynck, J. Boemmels, N. Collaert, N. Horiguchi","doi":"10.1109/VLSITechnology18217.2020.9265026","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265026","url":null,"abstract":"Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $(< 525^{circ}mathrm{C})$. Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $mathrm{I}_{mathrm{on}}-mathrm{I}_{mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91206490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. L. Jiang, M. S. Zaman, S. Murray, H. De Vleeschouwer, J. Roig, P. Moens, O. Trescases
{"title":"GaN PMIC Opportunities: Characterization of Analog and Digital Building Blocks in a 650V GaN-on-Si Platform","authors":"W. L. Jiang, M. S. Zaman, S. Murray, H. De Vleeschouwer, J. Roig, P. Moens, O. Trescases","doi":"10.1109/VLSITechnology18217.2020.9265112","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265112","url":null,"abstract":"This paper reports the performance of GaN -based building blocks for monolithic integration. An integrated gate driver, low-voltage analog and synchronous digital circuits are fabricated in a 650-V GaN-on-Si process and measured. Calibrated GaN models are compared against simulated silicon designs to identify optimal integration criteria.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"34 3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90454227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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