A. Gupta, H. Mertens, Z. Tao, S. Demuynck, J. Bömmels, G. Arutchelvan, K. Devriendt, O. Pedreira, R. Ritzenthaler, S. Wang, D. Radisic, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, H. Zahedmanesh, S. Subramanian, F. Schleicher, T. Hopf, A. Peter, N. Rassoul, H. Debruyn, I. Demonie, Y. Siew, T. Chiarella, B. Briggs, D. Zhou, E. Rosseel, A. De Keersgieter, E. Capogreco, E. Litta, G. Boccardi, S. Baudot, G. Mannaert, N. Bontemps, A. Sepúlveda, S. Mertens, M. Kim, E. Dupuy, K. Vandersmissen, S. Paolillo, D. Yakimets, B. Chehab, P. Favia, C. Drijbooms, J. Cousserier, M. Jaysankar, F. Lazzarino, P. Morin, E. Sanchez, J. Mitard, C. Wilson, F. Holsteyns, Z. Tökei, N. Horiguchi
{"title":"埋地电源轨集成与硅finfet的CMOS扩展超过5nm节点","authors":"A. Gupta, H. Mertens, Z. Tao, S. Demuynck, J. Bömmels, G. Arutchelvan, K. Devriendt, O. Pedreira, R. Ritzenthaler, S. Wang, D. Radisic, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, H. Zahedmanesh, S. Subramanian, F. Schleicher, T. Hopf, A. Peter, N. Rassoul, H. Debruyn, I. Demonie, Y. Siew, T. Chiarella, B. Briggs, D. Zhou, E. Rosseel, A. De Keersgieter, E. Capogreco, E. Litta, G. Boccardi, S. Baudot, G. Mannaert, N. Bontemps, A. Sepúlveda, S. Mertens, M. Kim, E. Dupuy, K. Vandersmissen, S. Paolillo, D. Yakimets, B. Chehab, P. Favia, C. Drijbooms, J. Cousserier, M. Jaysankar, F. Lazzarino, P. Morin, E. Sanchez, J. Mitard, C. Wilson, F. Holsteyns, Z. Tökei, N. Horiguchi","doi":"10.1109/VLSITechnology18217.2020.9265113","DOIUrl":null,"url":null,"abstract":"Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node\",\"authors\":\"A. Gupta, H. Mertens, Z. Tao, S. Demuynck, J. Bömmels, G. Arutchelvan, K. Devriendt, O. Pedreira, R. Ritzenthaler, S. Wang, D. Radisic, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, H. Zahedmanesh, S. Subramanian, F. Schleicher, T. Hopf, A. Peter, N. Rassoul, H. Debruyn, I. Demonie, Y. Siew, T. Chiarella, B. Briggs, D. Zhou, E. Rosseel, A. De Keersgieter, E. Capogreco, E. Litta, G. Boccardi, S. Baudot, G. Mannaert, N. Bontemps, A. Sepúlveda, S. Mertens, M. Kim, E. Dupuy, K. Vandersmissen, S. Paolillo, D. Yakimets, B. Chehab, P. Favia, C. Drijbooms, J. Cousserier, M. Jaysankar, F. Lazzarino, P. Morin, E. Sanchez, J. Mitard, C. Wilson, F. Holsteyns, Z. Tökei, N. Horiguchi\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265113\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"47 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265113\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
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