Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)

Abstract

A 12-high (12-Hi) die stack using low temperature SoIC bonding and stacking technology is presented and demonstrated for the application of HBM. The daisy chains in the 12-Hi structure incorporating over ten thousand TSVs and bonds are tested. Liner I-V curves are obtained to demonstrate the good bonding and stacking quality. The electrical link from a base logic die to top DRAM is built up to study the bandwidth and power consumption. Compared to $\mu \mathrm{bump}$ technology, the bandwidth for 12-Hi and 16-Hi structure using the SoIC technology shows the improvement of 18% and 20%, respectively and the power efficiency demonstrates the improvement of 8% and 15%, respectively. Also, the thermal performance for the 12-Hi and 16-Hi SoIC-bond structures are improved by 7% and 8%, respectively. Based on the proposed technologies, the scalability of bond pitch to sub-ten $\mu\mathrm{m}$ and die thickness to be thinner is prospected.