发布求助
文献互助 智能选刊 最新文献

2020 IEEE Symposium on VLSI Technology最新文献

筛选
英文 中文
Heterogeneous System-Level Package Integration - Trends and Challenges 异构系统级包集成——趋势与挑战
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265085
Frank J. C. Lee, Mei Wong, J. Tzou, J. Yuan, Daniel Chang, S. Rusu
{"title":"Heterogeneous System-Level Package Integration - Trends and Challenges","authors":"Frank J. C. Lee, Mei Wong, J. Tzou, J. Yuan, Daniel Chang, S. Rusu","doi":"10.1109/VLSITechnology18217.2020.9265085","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265085","url":null,"abstract":"Heterogeneous package-level integration plays an increasing role in higher functional density and lower power processors for general computing, machine learning and mobile applications. This paper will review technology trends and challenges for 2.5D and 3D package-level integration with special focus on system-technology co-optimization of the die partitioning, electrical interfaces, power delivery, thermal modeling and EDA flows.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"39 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78439683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing 一种基于差分行权映射的电压模式感知方案，用于高效的随机存储器内存计算
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265066
W. Wan, R. Kubendran, B. Gao, Siddharth Josbi, Priyanka Raina, Huaqiang Wu, G. Cauwenberghs, H. Wong
{"title":"A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing","authors":"W. Wan, R. Kubendran, B. Gao, Siddharth Josbi, Priyanka Raina, Huaqiang Wu, G. Cauwenberghs, H. Wong","doi":"10.1109/VLSITechnology18217.2020.9265066","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265066","url":null,"abstract":"The energy efficiency of RRAM-based in-memory matrix-vector multiplication (MVM) depends largely on the output sensing mechanism. We design a novel voltage-mode sensing configuration with differential-row weight mapping that achieves a 3.6x improvement in energy per multiply-accumulate (MAC) at the same read voltage compared to current-mode sensing, and avoids the nonlinear source-line dynamics issue that occurs in conventional voltage-mode sensing. We verify the MVM performance of our scheme by performing measurements using a RRAM array monolithically integrated with CMOS voltage-mode neurons. We compare the effects of weight normalization on MVM accuracy under two different weight mapping schemes, and provide guidance in selecting the scheme based on weight sparsity and consistency of the L-1 weight norm across the columns.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"9 1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88075050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Local Variation-Aware Transistor Design through Comprehensive Analysis of Various Vdd/Temperatures Using Sub- 7nm Advanced FinFET Technology 采用亚7nm先进FinFET技术综合分析不同Vdd/温度的局部变化感知晶体管设计
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265089
Soyoun Kim, S. Kim, Taiko Yamaguchi, Jae Chul Kim, Byung-Gook Park, Y. Y. Masuoka, S. Kwon
{"title":"Local Variation-Aware Transistor Design through Comprehensive Analysis of Various Vdd/Temperatures Using Sub- 7nm Advanced FinFET Technology","authors":"Soyoun Kim, S. Kim, Taiko Yamaguchi, Jae Chul Kim, Byung-Gook Park, Y. Y. Masuoka, S. Kwon","doi":"10.1109/VLSITechnology18217.2020.9265089","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265089","url":null,"abstract":"In this paper, key contributors to local variability of sub-7nm FinFET has been identified in various operating environments. Through a comprehensive analysis, different root-cause for high and low temperature region have been revealed and confirmed by advanced Si wafer for the first time. Moreover, a local variation-aware transistor was successfully demonstrated to reduce $sigma V_{mathrm{min}}$ distribution by 0.5 x and 0.3 x at cold temperature.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"61 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91348757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Record Low Contact Resistivity to Ge:B $(8.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$ and GeSn:B $(4.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$ with Optimized [B] and [Sn] by In-situ CVD Doping 通过原位CVD掺杂优化[B]和[Sn]，对Ge:B $(8.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$和GeSn:B $(4.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$的低接触电阻率记录
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265009
Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, C. Liu
{"title":"Record Low Contact Resistivity to Ge:B $(8.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$ and GeSn:B $(4.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$ with Optimized [B] and [Sn] by In-situ CVD Doping","authors":"Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, C. Liu","doi":"10.1109/VLSITechnology18217.2020.9265009","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265009","url":null,"abstract":"The record low contact resistivity <tex>$(rho_{mathrm{c}})$</tex> of Ti contact to Ge:B <tex>$(8.1mathrm{x}10^{-10}Omega-mathrm{cm}^{2})$</tex> is achieved by in-situ doped CVD using the high-order Ge precursor <tex>$(mathrm{Ge}_{2}mathrm{H}_{6})$</tex>. The best achievable <tex>$[mathrm{B}]_{mathrm{act}}$</tex>. of <tex>$7mathrm{x}10^{20}mathrm{cm}^{-3}$</tex> and extended epitaxial process window are obtained using <tex>$mathrm{Ge}_{2}mathrm{H}_{6}$</tex>. By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest <tex>$mathrm{p}_{mathrm{c}}$</tex> of <tex>$4.1mathrm{x}10^{-10} Omega-mathrm{cm}^{2}$</tex>. Further Sn addition (4.7% and 13.2%) increases <tex>$rho_{mathrm{c}}$</tex> due to reduced [B], and degrades the thermal stability. The record low resistivity <tex>$(2mathrm{x}10^{-4}Omega-mathrm{cm})$</tex> among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes (<tex>$mathrm{Cl}_{2}+mathrm{BCl}_{3}$</tex> for metal on <tex>$mathrm{GeSn}:mathrm{B}$</tex>, while <tex>$mathrm{C}1_{2}$</tex> for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the <tex>$rho_{mathrm{c}}$</tex>. B segregation <tex>$(> 1mathrm{x}10^{21}mathrm{cm}^{-3})$</tex> at the metal/semiconductor interface enables the record low <tex>$rho_{mathrm{c}}$</tex>.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"35 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89418520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-Software Co-integration for Configurable 5G mmWave Systems 可配置5G毫米波系统的软硬件协集成
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265032
A. Valdes-Garcia, A. Paidimarri, B. Sadhu
{"title":"Hardware-Software Co-integration for Configurable 5G mmWave Systems","authors":"A. Valdes-Garcia, A. Paidimarri, B. Sadhu","doi":"10.1109/VLSITechnology18217.2020.9265032","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265032","url":null,"abstract":"Directional communication systems based on millimeter-wave phased arrays have reached a significant level of maturity and have entered the commercial space for 5G networks. In order to realize their full potential, Si -based phased arrays must be integrated efficiently at the system level with digital control electronics, firmware, and software. This paper describes key architecture approaches for such vertical integration from digital-RF co-integration in the IC to API definition in software. The important benefits of low-latency and versatile control of beam forming and radio functions from high-level APIs is illustrated with application examples at 28 GHz including directional channel sounding, spatio-temporal beamforming, and 3D imaging.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"8 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82189270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FinFET with Contact over Active-Gate for 5G Ultra-Wideband Applications 5G超宽带应用的有源门接触FinFET
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265095
A. Razavieh, V. Mahajan, W. L. Oo, S. Cimino, S. Khokale, K. Nagahiro, L. Pantisano, T. Ethirajan, J. Lemon, M. Gu, Y. Chen, H. Wang, T. H. Lee
{"title":"FinFET with Contact over Active-Gate for 5G Ultra-Wideband Applications","authors":"A. Razavieh, V. Mahajan, W. L. Oo, S. Cimino, S. Khokale, K. Nagahiro, L. Pantisano, T. Ethirajan, J. Lemon, M. Gu, Y. Chen, H. Wang, T. H. Lee","doi":"10.1109/VLSITechnology18217.2020.9265095","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265095","url":null,"abstract":"FinFET with contact over active-gate (COAG) is implemented on 12nm node technology platform to optimize the Maximum Oscillation Frequency $(F_{MAX})$) and the Minimum Noise Figure $(NF_{MIN}$ for devices with large fin numbers. This study shows that proposed COAG design can reduce the gate resistance of the 40-fin device by ~ 10- fold, while improving the $F_{MAX}$ by ~ 180% with comparable reliability performance to traditional FinFETs. Excellent DC and RF performances with $NF_{MIN}$ of 0.6dB at 26GHz and 3dB improvement in NF with $50mathrm{Q}$ source impedance $(NF_{50}$) over the 5-26GHz frequency range makes large fin number COAG FinFET an excellent candidate for variety of 5G sub-6GHz and mmWave applications in which high $mathrm{F}_{mathrm{MAX}}$ and low noise are critical.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79513668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Composite Interconnects for High-Performance Computing Beyond the 7nm Node 7nm以上节点的高性能计算复合互连
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265021
P. Bhosale, S. Parikh, N. Lanzillo, R. Tao, T. Nogami, M. Gage, R. Shaviv, H. Huang, A. Simon, M. Stolfi, S. Reidy, J. Lee, N. Loubet, B. Haran
{"title":"Composite Interconnects for High-Performance Computing Beyond the 7nm Node","authors":"P. Bhosale, S. Parikh, N. Lanzillo, R. Tao, T. Nogami, M. Gage, R. Shaviv, H. Huang, A. Simon, M. Stolfi, S. Reidy, J. Lee, N. Loubet, B. Haran","doi":"10.1109/VLSITechnology18217.2020.9265021","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265021","url":null,"abstract":"We demonstrate a design-technology co-optimization (DTCO) solution for enabling novel composite interconnects in next-generation high-performance computing (HPC) applications. Minimum-pitch signal line optimization with aggressively shrunk feature size potentially requires a non-Cu conductor while relaxed-pitch signal and power line optimization require traditional Cu metallization, along with properly tuned power tap spacing, activity factor and standard cell size. We discuss significant process innovation required to co-optimize signal and power line resistances. Our composite metallization scheme also reduces via resistance by 50%, which results in a net performance uplift of between 2%-10% depending on via density and power requirements. We believe this is an optimal approach for HPC applications that have implemented alternate, higher-resistivity conductor metals at the 1x levels","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"96 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75023745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Understanding of Tunable Selector Performance in Si-Ge-As-Se OTS Devices by Extended Percolation Cluster Model Considering Operation Scheme and Material Design 考虑操作方案和材料设计的扩展渗透簇模型理解Si-Ge-As-Se OTS器件的可调选择器性能
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265011
S. Kabuyanagi, D. Garbin, A. Fantini, S. Clima, R. Degraeve, G. Donadio, W. Devulder, R. Delhougne, D. Cellier, A. Cockburn, W. Kim, M. Pakala, M. Suzuki, L. Goux, G. Kar
{"title":"Understanding of Tunable Selector Performance in Si-Ge-As-Se OTS Devices by Extended Percolation Cluster Model Considering Operation Scheme and Material Design","authors":"S. Kabuyanagi, D. Garbin, A. Fantini, S. Clima, R. Degraeve, G. Donadio, W. Devulder, R. Delhougne, D. Cellier, A. Cockburn, W. Kim, M. Pakala, M. Suzuki, L. Goux, G. Kar","doi":"10.1109/VLSITechnology18217.2020.9265011","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265011","url":null,"abstract":"Switching mechanism and its controllability in Ovonic Threshold Switching (OTS) devices are systematically investigated by using Si-Ge-As-Se quaternary system known as promising OTS materials. We newly demonstrate that selector device performance is flexibly tunable by controlling fall time of switching pulse as well as operation current. Meanwhile, As- and Si-incorporation are found to be beneficial in terms of stable operation and faster recovery. All results are consistently understandable by extended percolation cluster model, supported by ab-initio and Monte-Carlo simulations.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"66 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75092548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Improved state stability of HfO2 ferroelectric tunnel junction by template-induced crystallization and remote scavenging for efficient in-memory reinforcement learning 通过模板诱导结晶和远程清除提高HfO2铁电隧道结的状态稳定性，实现有效的内存强化学习
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265059
S. Fujii, M. Yamaguchi, S. Kabuyanagi, K. Ota, M. Saitoh
{"title":"Improved state stability of HfO2 ferroelectric tunnel junction by template-induced crystallization and remote scavenging for efficient in-memory reinforcement learning","authors":"S. Fujii, M. Yamaguchi, S. Kabuyanagi, K. Ota, M. Saitoh","doi":"10.1109/VLSITechnology18217.2020.9265059","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265059","url":null,"abstract":"We investigated the effects of read current instabilities originated from depolarization field and charge trapping in HfO2 ferroelectric tunnel junctions (FTJs) on the performance of in-memory reinforcement learning. We utilized, for the first time, remote scavenging to control interfacial layer thickness, combined with template-induced crystallization to stabilize the ferroelectric phase. These are found to improve both short-term and long-term stability of memory state. Pole-cart simulation results reveal that these improvements significantly contribute to the efficiency and stability of reinforcement learning with the FTJ cross-point array.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"56 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73842515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices PMOS层叠纳米片栅极全能器件SiGe包层通道的结构与电学论证
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265097
S. Mochizuki, B. Colombeau, J. Zhang, S. Kung, M. Stolfi, H. Zhou, M. Breton, K. Watanabe, J. Li, H. Jagannathan, M. Cogorno, T. Mandrekar, P. Chen, N. Loubet, S. Natarajan, B. Haran
{"title":"Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices","authors":"S. Mochizuki, B. Colombeau, J. Zhang, S. Kung, M. Stolfi, H. Zhou, M. Breton, K. Watanabe, J. Li, H. Jagannathan, M. Cogorno, T. Mandrekar, P. Chen, N. Loubet, S. Natarajan, B. Haran","doi":"10.1109/VLSITechnology18217.2020.9265097","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265097","url":null,"abstract":"In this paper, horizontal gate-all-around (hGAA) devices with a SiGe cladded nanosheet (NS) channel have been explored for their potential benefits of Vt modulation and improved NBTI. The SiGe cladded NS channel was formed through trimming of the Si NS channel followed by selective SiGe epitaxial growth. Selective Si NS channel trimming of 1 - 2 nm per side with low roughness and conformal SiGe cladding epitaxial growth of 2 - 3 nm with good crystallinity were demonstrated. It is shown that a SiGe cladding NS channel provides a reduction of threshold voltage (Vt) and improved reliability. It is also shown that a conformal Si cap grown on the SiGe cladded NS channel suppresses the interface trap density (Dit).","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"100 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80745792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信