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2020 IEEE Symposium on VLSI Technology最新文献

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Surface Ga-boosted Boron-doped $mathrm{Si}_{0.5}mathrm{Geo}_{0.5}$ using In-situ CVD Epitaxy: Achieving $1.1 times 10^{21}mathrm{cm}^{-3}$ Active Doping Concentration and $5.7times 10^{-10}Omega-mathrm{cm}^{2}$ Contact Resistivity 利用原位CVD外延技术实现$1.1 乘以10^{21} mathm {cm}^{-3}$活性掺杂浓度和$5.7乘以10^{-10}Omega- mathm {cm}^{2}$接触电阻率
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265058
Haiwen Xu, Jishen Zhang, L. Lima, J. Margetis, R. Khazaka, Q. Xie, J. Tolle, Chengkuan Wang, Haibo Wang, Zuopu Zhou, Qiwen Kong, X. Gong
{"title":"Surface Ga-boosted Boron-doped $mathrm{Si}_{0.5}mathrm{Geo}_{0.5}$ using In-situ CVD Epitaxy: Achieving $1.1 times 10^{21}mathrm{cm}^{-3}$ Active Doping Concentration and $5.7times 10^{-10}Omega-mathrm{cm}^{2}$ Contact Resistivity","authors":"Haiwen Xu, Jishen Zhang, L. Lima, J. Margetis, R. Khazaka, Q. Xie, J. Tolle, Chengkuan Wang, Haibo Wang, Zuopu Zhou, Qiwen Kong, X. Gong","doi":"10.1109/VLSITechnology18217.2020.9265058","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265058","url":null,"abstract":"For the first time, we have achieved contact resistivity <tex>$(p_{c}$</tex>) less than 10<inf>−9</inf> Ω-cm<inf>2</inf> for p-type metal/Si<inf>1-x</inf>Ge<inf>x</inf> contacts with in-situ doping-only technique. This is enabled by an optimized surface Gallium (Ga)-boosted Boron (B)-doped <tex>$mathrm{Si}_{0.5}mathrm{Ge}_{0.5}$</tex> having active doping concentration <tex>$(N_{a})$</tex> of <tex>$1.1 times 10^{21}$</tex> cm<inf>−3</inf> grown using reduced pressure chemical vapour deposition (RPCVD). Compared with B-only doped sample with <tex>$N_{a}$</tex> of <tex>$9times 10^{20}mathrm{cm}^{-3}$</tex> B and Ga codoping enhances <tex>$N_{a}$</tex> by <tex>$2times 10^{20} mathrm{cm}^{-3}$</tex> reducing <tex>$rho_{c}$</tex> from <tex>$1.5times 10^{-9}Omega-mathrm{cm}^{2}$</tex> to 5.7 <tex>$times 10^{10}Omega-mathrm{cm}^{2}. rho c$</tex> was extracted using advanced ladder transmission line model (LTLM) structures. It was also found that sub- <tex>$10^{9}Omega-mathrm{cm}^{2}rho_{c}$</tex> of our <tex>$mathrm{Ti}/mathrm{Si}_{0.5}mathrm{Ge}_{0.5}$</tex> contact can be maintained with thermal budget up to 450°C.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"81 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81001658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Executive Committee IEEE执行委员会
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/icmete.2016.147
H. Wong, A. Amerasekera, A. Chandrakasan, A. Cathelin, Vivek De, Fariborz Assaderaghi, Gary Patton, Gunther Lehmann, Hans Stork, Ichiro Fujimori, R. Jammy, Jason Woo, J. Gealow, Kaizad Mistry, Katsu Nakamura, K. Schruefer, Mukesh V. Khare, S. Kosonocky, Tsu-Jae
{"title":"IEEE Executive Committee","authors":"H. Wong, A. Amerasekera, A. Chandrakasan, A. Cathelin, Vivek De, Fariborz Assaderaghi, Gary Patton, Gunther Lehmann, Hans Stork, Ichiro Fujimori, R. Jammy, Jason Woo, J. Gealow, Kaizad Mistry, Katsu Nakamura, K. Schruefer, Mukesh V. Khare, S. Kosonocky, Tsu-Jae","doi":"10.1109/icmete.2016.147","DOIUrl":"https://doi.org/10.1109/icmete.2016.147","url":null,"abstract":"Members Ajith Amerasekera Anantha Chandrakasan Andreia Cathelin Vivek De Fariborz Assaderaghi Gary Patton Gunther Lehmann Hans Stork Ichiro Fujimori Raj Jammy Jason Woo Jeffrey Gealow Kaizad Mistry Katsu Nakamura Klaus Schruefer Mukesh Khare Stephen Kosonocky Tsu-Jae King University of California Massachusetts Institute of Technology STMicroelectronics Intel NXP Global Foundries Infineon ON Semiconductor Broadcom ZEISS University of California Analog Devices Intel Analog Devices Intel IBM AMD University of California","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"111 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86052681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Buried power SRAM DTCO and system-level benchmarking in N3 N3中埋电SRAM DTCO和系统级基准测试
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265076
S. Salahuddin, M. Perumkunnil, E. Litta, A. Gupta, P. Weckx, J. Ryckaert, M. Na, A. Spessot
{"title":"Buried power SRAM DTCO and system-level benchmarking in N3","authors":"S. Salahuddin, M. Perumkunnil, E. Litta, A. Gupta, P. Weckx, J. Ryckaert, M. Na, A. Spessot","doi":"10.1109/VLSITechnology18217.2020.9265076","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265076","url":null,"abstract":"The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as SRAM performance and write ability booster in 3nm node. BPR-SRAM offers up to 34.5% read speed and 498.6mV write margin improvement over conventional SRAM. Gem5 system simulator predicts up to 28.2% performance gain with server-processor having BPR-SRAM in L2 and L3 cache as compared to the baseline.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"20 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85255045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineerlng Using High-k AlON 基于高k光接口工程的大内存窗口和长脉冲循环耐用性的ffet存储器
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265103
C. Chan, Kuen-Yi Chen, Hao-Kai Peng, Yung-Hsien Wu
{"title":"FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineerlng Using High-k AlON","authors":"C. Chan, Kuen-Yi Chen, Hao-Kai Peng, Yung-Hsien Wu","doi":"10.1109/VLSITechnology18217.2020.9265103","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265103","url":null,"abstract":"Without destabilizing the ferroelectric (FE) phase, high-k AlON with [N] of ~ 13 % was proposed as the interfacial layer (IL) between FE HfZrOx (HZO) and Si substrate for FeFET memory to enhance the memory window (MW) while improving reliability compared to SiO2 IL. The AlON-based memory shows promising performance in terms of a large MW of 3.1 V by ±4 V operation, long retention up to 10 years, and robust endurance up to 105 cycles with a long pulse width of 10−4 s, outstanding other FeFET memory devices. It is ascribed to the high k value and larger ΔEv that respectively allow a lower voltage drop across the IL and suppress hole trapping. [N] in the IL also enhances the thermal stability that Inhibits sub-IL formation by restraining the reaction of residual OH groups with Si substrate. Besides, the AlON and FE-HZO can be integrated in a single ALD step to simplify the process. From device performance and process viewpoints, AlON paves a promising avenue to enable more reliable and feasible FeFET memory.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81033358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Fast Thermal Quenching on the Ferroelectric Al:HfO2 Thin Film with Record Polarization Density and Flash Memory Application 高极化密度铁电Al:HfO2薄膜的快速热猝灭及其在闪存中的应用
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265024
B. Ku, Seonjun Choi, Y. Song, C. Choi
{"title":"Fast Thermal Quenching on the Ferroelectric Al:HfO2 Thin Film with Record Polarization Density and Flash Memory Application","authors":"B. Ku, Seonjun Choi, Y. Song, C. Choi","doi":"10.1109/VLSITechnology18217.2020.9265024","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265024","url":null,"abstract":"We have investigated the effects of post cooling process with chamber cooling, air cooling and fast quenching in DI water on the ferroelectric (FE) characteristics of Al-doped Hf0<inf>2</inf> (Al:HfO<inf>2</inf>) thin films and demonstrated their potential flash memory applications. Compared with other cooling processes, using fast quenching after annealing we achieved the drastic increase of remnant polarization <tex>$(mathrm{P}_{mathrm{r}})$</tex> and coercive electric field <tex>$(mathrm{E}_{mathrm{c}})$</tex>. The highest <tex>$2mathrm{P}_{mathrm{r}}$</tex> and <tex>$2mathrm{E}_{mathrm{c}}$</tex> are <tex>$sim 100mumathrm{C}/mathrm{cm}^{2}$</tex> and ~9.5 MV/cm, respectively, the highest records among HfO<inf>2</inf>-based FE reported so far. These improvements are attributed to induce higher stress/strain within A1:HfO<inf>2</inf> thin film, leading to stable orthorhombic phase (o-phase). Program/erase up to 10<inf>6</inf> cycles and 10 years retention characteristics are also evaluated for the potential flash memory application. Our simulation with experimental data indicates that P<inf>r</inf> and E<inf>c</inf> significantly can influence on the memory window and multi-bit states, which can be tuned by our proposed quenching process.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"4 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80895573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Materials Technology Co-optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes 先进CMOS技术节点自对准栅极触点的材料技术协同优化
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265043
A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari
{"title":"Materials Technology Co-optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes","authors":"A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari","doi":"10.1109/VLSITechnology18217.2020.9265043","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265043","url":null,"abstract":"Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"222 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79925271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Empowering Next-Generation Applications through FLASH Innovation 通过FLASH创新为下一代应用程序赋能
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265031
Shigeo Ohshima
{"title":"Empowering Next-Generation Applications through FLASH Innovation","authors":"Shigeo Ohshima","doi":"10.1109/VLSITechnology18217.2020.9265031","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265031","url":null,"abstract":"The flash industry has continuously produced game-changing innovations in density, latency, and form factors resulting in large cost-performance benefits. To address the wide spectrum of storage demands coming from phone/IoT devices, mobile compute, up to data centers, new flash architectures are essential to handle these next generation applications. Future technology must include not only new architectures and more layers in flash chip designs, but also a roadmap for QLC flash and beyond, new memories, new classes of SSDs, and new software technologies. They must all come together to enable and accelerate the next wave of applications including the real-time analytics, AI (Artificial Intelligence)/ML (Machine Learning), high-performance computing, IoT, and virtual and augmented reality.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76952679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BEOL Compatible Dual-Gate Ultra Thin-Body W-Doped Indium-Oxide Transistor with Ion = 370μA/μm, SS = 73mV/dec and Ion /Ioff Ratio > 4×109 BEOL兼容双栅超薄体掺w氧化铟晶体管，离子= 370μA/μm, SS = 73mV/dec，离子/开关比> 4×109
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/vlsitechnology18217.2020.9265064
W. Chakraborty, B. Grisafe, H. Ye, I. Lightcap, Kaiwen Ni, S. Datta
{"title":"BEOL Compatible Dual-Gate Ultra Thin-Body W-Doped Indium-Oxide Transistor with Ion = 370μA/μm, SS = 73mV/dec and Ion /Ioff Ratio > 4×109","authors":"W. Chakraborty, B. Grisafe, H. Ye, I. Lightcap, Kaiwen Ni, S. Datta","doi":"10.1109/vlsitechnology18217.2020.9265064","DOIUrl":"https://doi.org/10.1109/vlsitechnology18217.2020.9265064","url":null,"abstract":"","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"51 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78302672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
5G Evolution and 6G 5G演进和6G
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265094
Takehiro Nakamura
{"title":"5G Evolution and 6G","authors":"Takehiro Nakamura","doi":"10.1109/VLSITechnology18217.2020.9265094","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265094","url":null,"abstract":"In this paper, SG evolution, which is the enhancement of SG, and the direction of the evolution of mobile communication technologies for 6G assuming the society and the worldview in the 2030s are examined, and requirements, use cases, and concepts pertaining to technical examination are described [1].","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73607798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
A SiOx, RRAM-based hardware with spike frequency adaptation for power-saving continual learning in convolutional neural networks 一种基于SiOx, rram的硬件，具有尖峰频率自适应，用于卷积神经网络的节能持续学习
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265072
I. Muñoz-Martín, S. Bianchi, E. Covi, G. Piccolboni, A. Bricalli, A. Regev, J. Nodin, E. Nowak, G. Molas, D. Ielmini
{"title":"A SiOx, RRAM-based hardware with spike frequency adaptation for power-saving continual learning in convolutional neural networks","authors":"I. Muñoz-Martín, S. Bianchi, E. Covi, G. Piccolboni, A. Bricalli, A. Regev, J. Nodin, E. Nowak, G. Molas, D. Ielmini","doi":"10.1109/VLSITechnology18217.2020.9265072","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265072","url":null,"abstract":"Biological systems autonomously evolve to maximize their efficiency in a continually changing world. On the other hand, artificial neural networks (ANNs) outperform the human ability of object recognition but cannot acquire new information without forgetting trained tasks. To introduce resilience in ANNs, we present a SiOx RRAM-based inference hardware capable of merging the efficiency of convolutional ANNs and the plasticity of spiking networks. We validate the accuracy of the system with MNIST (99.3%), noisyN-MNIST (96%), Fashion-MNIST (93%) and CIFAR-10 (91 %) datasets. We demonstrate that the circuit plastically adapts its operative frequency for power saving and enables continual learning of up to 50% non-trained classes. This optimizes the classification and enables the re-training of the filters, thus overcoming the catastrophic forgetting of standard ANN s.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"58 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80510801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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