先进CMOS技术节点自对准栅极触点的材料技术协同优化

2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI:10.1109/VLSITechnology18217.2020.9265043

A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari

{"title":"先进CMOS技术节点自对准栅极触点的材料技术协同优化","authors":"A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari","doi":"10.1109/VLSITechnology18217.2020.9265043","DOIUrl":null,"url":null,"abstract":"Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"222 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Materials Technology Co-optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes\",\"authors\":\"A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265043\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"222 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265043\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265043","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

材料技术协同优化(MTCO)模型首次用于模拟自对准栅极接触(SAGC)技术的性能-功率-面积(PPA)效益。我们还演示了一种集成新型CMOS兼容材料和工艺的工艺流程，以实现3nm及以下节点的SAGC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Materials Technology Co-optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes

Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2020 IEEE Symposium on VLSI Technology

自引率

0.00%

发文量