Yu-Shiang Huang, Fang-Liang Lu, Chien-Te Tu, Jyun-Yan Chen, Chung-En Tsai, Hung-Yu Ye, Yi-Chun Liu, C. Liu
{"title":"First Demonstration of 4-Stacked Ge0.915Sn0.085 Wide Nanosheets by Highly Selective Isotropic Dry Etching with High S/D Doping and Undoned Channels","authors":"Yu-Shiang Huang, Fang-Liang Lu, Chien-Te Tu, Jyun-Yan Chen, Chung-En Tsai, Hung-Yu Ye, Yi-Chun Liu, C. Liu","doi":"10.1109/VLSITechnology18217.2020.9265056","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265056","url":null,"abstract":"The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $mathrm{I}_{mathrm{O}mathrm{N}}=42mu 1$ per stack ($10.5mu A$. per sheet) at $mathrm{V}_{mathrm{OV}}mathrm{V}_{mathrm{DS}}=-0.5mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"30 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73570743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Cheng, I. Kuo, W. Chien, C. Yeh, Y. Chou, N. Gong, L. Gignac, C. Yang, C. Cheng, C. Lavoie, M. Hopstaken, R. Bruce, L. Buzi, E. Lai, F. Carta, A. Ray, M. Lee, H. Ho, W. Kim, M. BrightSky, H. Lung
{"title":"Si Incorporation Into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low $mathrm{V}_{mathrm{th}}$ Drift 3D Stackable Cross-point Memory : IBM/Macronix PCRAM Joint Project","authors":"H. Cheng, I. Kuo, W. Chien, C. Yeh, Y. Chou, N. Gong, L. Gignac, C. Yang, C. Cheng, C. Lavoie, M. Hopstaken, R. Bruce, L. Buzi, E. Lai, F. Carta, A. Ray, M. Lee, H. Ho, W. Kim, M. BrightSky, H. Lung","doi":"10.1109/VLSITechnology18217.2020.9265039","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265039","url":null,"abstract":"By incorporating Si into AsSeGe system, we demonstrate a 3D stackable OTS+PCM memory in a 1k by 1k cross-point memory array with extremely low $mathrm{V}_{mathrm{tS}}$ drift (~0V after 3 days from programming), wide $mathrm{V}_{mathrm{tS}}/mathrm{V}_{mathrm{tR}}$ window (>2V main distribution memory window), high endurance (>2E11 cycles), excellent $mathrm{I}_{mathrm{OFF}}$ and thermal stability. So far, attempts to improve the thermal stability of AsSeGe system sacrifice $mathrm{I}_{mathrm{OFF}}$ and cycling endurance. We show that Si incorporation relaxes this trade-off and can greatly improve the thermal stability and cycling endurance while also achieving good $mathrm{I}_{mathrm{OFF}}$. In particular the $mathrm{I}_{mathrm{OFF}}$ of AsSeGeSi selector is improved over the AsSeGe system for films of 20 nm.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"4 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74490264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Porret, S. Srinivasan, S. Balakrishnan, P. Verheyen, P. Favia, H. Bender, P. Ong, R. Loo, J. Van Campenhout, M. Pantouvaki
{"title":"O-band GeSi quantum-confined Stark effect electro-absorption modulator integrated in a 220nm silicon photonics platform","authors":"C. Porret, S. Srinivasan, S. Balakrishnan, P. Verheyen, P. Favia, H. Bender, P. Ong, R. Loo, J. Van Campenhout, M. Pantouvaki","doi":"10.1109/VLSITechnology18217.2020.9265082","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265082","url":null,"abstract":"We report on a waveguide-coupled quantum-confined Stark effect (QCSE) electro-absorption modulator integrated in a 220nm Si photonics platform and operating in 1335-1365nm wavelength range. The device is based on a strain -balanced GeSi quantum well / barrier stack grown on an ultra-thin strain-relaxed buffer. The stack is only 450nm thick, facilitating optical coupling to sub-micron Si waveguides. An extinction ratio up to 8dB is achieved in a $40mu mathrm{m}$ long device for a 1 Vpp drive voltage, demonstrating the potential of this modulator for low-power optical interconnect applications.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78034303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Chiang, T. C. Chen, J. F. Wang, S. Mukhopadhyay, W. K. Lee, C. Chen, W. Khwa, B. Pulicherla, P. Liao, K. Su, K. F. Yu, T. Wang, H. P. Wong, C. Diaz, J. Cai
{"title":"Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs","authors":"H. Chiang, T. C. Chen, J. F. Wang, S. Mukhopadhyay, W. K. Lee, C. Chen, W. Khwa, B. Pulicherla, P. Liao, K. Su, K. F. Yu, T. Wang, H. P. Wong, C. Diaz, J. Cai","doi":"10.1109/VLSITechnology18217.2020.9265065","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265065","url":null,"abstract":"We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage $(V_{mathrm{TH}})$ and supply voltage $(V_{mathrm{DD}})$ scaling for $sim 0.27times$ power reduction without sacrificing logic switching speed. With simultaneous $V_{mathrm{TH}}$ scaling, SRAM can operate at the same low $V_{mathrm{DD}}$ of 0 4V. Improved gate dielectric reliability raises maximum $V_{mathrm{DE}}$ for $gt; 70%$ speed boost when single thread performance is needed. Taking advantage of lower Cu wire resistance at 77 K, the repeaters for global signal propagation can be redesigned for 80% energy reduction. Increased thermal conductivity of silicon at low temperature reduces self-heating and further improves power efficiency. When refrigeration power is included, net power reduction can be achieved when cooling efficiency exceeds $sim$ 50% of Carnot limit. We present effective $V_{mathrm{TH}}$ reduction methods for both nFET and pFET, critical for attaining high performance for cold CMOS.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77044581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen Sun, Daniel Jeong, Mason Zhang, Woorham Bae, Chong Zhang, Pavan Bhargava, D. Van Orden, S. Ardalan, C. Ramamurthy, E. Anderson, Austin Katzin, Haiwei Lu, S. Buchbinder, Behrooz Beheshtian, A. Khilo, M. Rust, Chen Li, Forrest Sedgwick, J. Fini, Roy Meade, V. Stojanović, M. Wade
{"title":"TeraPHY: An O-band WDM Electro-optic Platform for Low Power, Terabit/s Optical I/O","authors":"Chen Sun, Daniel Jeong, Mason Zhang, Woorham Bae, Chong Zhang, Pavan Bhargava, D. Van Orden, S. Ardalan, C. Ramamurthy, E. Anderson, Austin Katzin, Haiwei Lu, S. Buchbinder, Behrooz Beheshtian, A. Khilo, M. Rust, Chen Li, Forrest Sedgwick, J. Fini, Roy Meade, V. Stojanović, M. Wade","doi":"10.1109/VLSITechnology18217.2020.9265012","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265012","url":null,"abstract":"We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The $5.5mathrm{x}8.9mathrm{mm}^{2}$ chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and integrates high-speed digital/analog circuits, optical modulators, photodetectors, and waveguides. Transmitters and receivers demonstrate data-rates up to 25Gbps at 4.9pJ/bit (Tx+Rx) and <10−12 BER error-free operation. We show a 32-channel, 512Gbps aggregate (across 4 Tx ports) wavelength-division multiplexed (WDM) transmit demonstration from a TeraPHY chiplet, running at 16Gbps per wavelength and 8 simultaneous wavelengths per port.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"64 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84054199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jin, K. Kim, B. Kim, M. Kim, S. Kwon, Y. Cho, M. Lee, T. Jeong, M. Yeo, K. Choi, H. Sagong, T. Uemura, H. Jiang, D. Mun, W. Kim, E. Kwon, Y. Kim, H. Shim, H. Nam, J. Park, H. Rhee, S. Pae, B. Lee
{"title":"A Comprehensive Reliability Characterization of 5G SoC Mobile Platform featuring 7nm EUV Process Technology","authors":"M. Jin, K. Kim, B. Kim, M. Kim, S. Kwon, Y. Cho, M. Lee, T. Jeong, M. Yeo, K. Choi, H. Sagong, T. Uemura, H. Jiang, D. Mun, W. Kim, E. Kwon, Y. Kim, H. Shim, H. Nam, J. Park, H. Rhee, S. Pae, B. Lee","doi":"10.1109/VLSITechnology18217.2020.9265018","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265018","url":null,"abstract":"The product reliability of 7nm FinFET technology is demonstrated with 5G SoC platform. RO aging and other highspeed operating 5G IPs show an expected reliability model behavior, which has further improvement of frequency noise reduction through 3-plate MIM integration and high thermal conductivity EMC featuring ultra-low alpha particle (<0.002cph/cm2) emitter for the encapsulation of 5G product. Radiation effects are extensively examined at both chip and transistor level, proving the excellent SER and SEL due to less charge collection in narrow fin and robust TID effect. Degradation of 6T SRAM cell stability and performance caused by BTI is comparable to previous 10nm technology. Product level reliability is further evaluated through 256Mb SRAM array and AP/Modem for mmWave 5G connectivity. The current 7nm technology featuring EUV is being expanded to automotive, HPC and AI beyond high volume 5G system.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"120 32","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91408103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Khanna, Eslam Elmitwalli, S. Dutta, Shan Deng, S. Datta, Selçuk Köse, K. Ni
{"title":"A Bias and Correlation Free True Random Number Generator Based on Quantized Oscillator Phase under Sub-Harmonic Injection Locking","authors":"A. Khanna, Eslam Elmitwalli, S. Dutta, Shan Deng, S. Datta, Selçuk Köse, K. Ni","doi":"10.1109/VLSITechnology18217.2020.9265106","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265106","url":null,"abstract":"In this work, we demonstrated a novel oscillator phase based true random number generator (TRNG) design that can be high speed, and bias and correlation free. We are showing that: i) the arbitrary phase difference between the unsynchronized oscillator and injected synchronization signal is collapsed into two random and stable phases under subharmonic injection locking (SHIL); ii) the quantized oscillator phases under SHIL are fully symmetric and memoryless, generating bias and correlation free random bits; iii) the proposed oscillator phase TRNG is a generic design, independent of the oscillator platform. Thus, a CMOS ring oscillator based TRNG is also designed and evaluated. All of the generated random numbers pass the National Institute of Standards and Technology (NIST) tests and exhibit negligible bias and correlation from statistical analysis. Therefore, the proposed solution provides a competitive alternative to the existing on-chip TRNG design toolbox.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"134 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79439378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Barraud, B. Previtali, C. Vizioz, J. Hartmann, J. Sturm, J. Lassarre, C. Perrot, P. Rodriguez, V. Loup, A. Magalhaes-Lucas, R. Kies, G. Romano, M. Cassé, N. Bernier, A. Jannaud, A. Grenier, F. Andrieu
{"title":"7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing","authors":"S. Barraud, B. Previtali, C. Vizioz, J. Hartmann, J. Sturm, J. Lassarre, C. Perrot, P. Rodriguez, V. Loup, A. Magalhaes-Lucas, R. Kies, G. Romano, M. Cassé, N. Bernier, A. Jannaud, A. Grenier, F. Andrieu","doi":"10.1109/VLSITechnology18217.2020.9265025","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265025","url":null,"abstract":"In this paper, we experimentally demonstrate, for the first time, gate-all-around (GAA) nanosheet transistors with a record number of stacked channels. Seven levels stacked nanosheet (NS) GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show an excellent gate controllability with extremely high current drivability $(3mathrm{mA}/mu mathrm{m} mathrm{at} mathrm{V}_{mathrm{DD}}=1mathrm{V})$ and a 3 x improvement in drain current over usual 2 levels stacked- NS GAA transistors.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78719308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Cheng, Chanro Park, Heng Wu, Juntao Li, S. Nguyen, Jingyun Zhang, Miaomiao Wang, S. Mehta, Zuoguang Liu, R. Conti, N. Loubet, J. Frougier, A. Greene, T. Yamashita, B. Haran, R. Divakaruni
{"title":"Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology","authors":"K. Cheng, Chanro Park, Heng Wu, Juntao Li, S. Nguyen, Jingyun Zhang, Miaomiao Wang, S. Mehta, Zuoguang Liu, R. Conti, N. Loubet, J. Frougier, A. Greene, T. Yamashita, B. Haran, R. Divakaruni","doi":"10.1109/VLSITechnology18217.2020.9265096","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265096","url":null,"abstract":"We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1984 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90342499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-Probe Characterization of Ferroelectric/Dielectric Interface by C-V, P-V and Conductance Methods","authors":"Junkang Li, Y. Qu, M. Si, X. Lyu, P. Ye","doi":"10.1109/VLSITechnology18217.2020.9265069","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265069","url":null,"abstract":"In this work, we report on the multi-probe characterization of interfacial charges at the ferroelectric/dielectric (FE/DE) interface in response to both large-signal measurement associated with polarization switching and small-signal measurement without polarization switching. Charge densities at the FE/DE interface are extracted from temperature dependent C-V, P-V, conductance methods. It is found that the charge injection and accumulation at the FE/DE interface play a key role in the operation of FE/DE stack. These enormous trapped charges of 1013-1014 cm-2 at the FE/DE interface are supplied from the leakage current through the ultrathin DE layer. The proposed multi-probe measurement techniques provide a comprehensive understanding of FE/DE stack. The demonstrated leakage-assist polarization switching provides the new insights on the understanding of negative-capacitance (NC) effect and ferroelectric device performance.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75709444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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