Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage $(V_{\mathrm{TH}})$ and supply voltage $(V_{\mathrm{DD}})$ scaling for $\sim 0.27\times$ power reduction without sacrificing logic switching speed. With simultaneous $V_{\mathrm{TH}}$ scaling, SRAM can operate at the same low $V_{\mathrm{DD}}$ of 0 4V. Improved gate dielectric reliability raises maximum $V_{\mathrm{DE}}$ for $gt; 70\%$ speed boost when single thread performance is needed. Taking advantage of lower Cu wire resistance at 77 K, the repeaters for global signal propagation can be redesigned for 80% energy reduction. Increased thermal conductivity of silicon at low temperature reduces self-heating and further improves power efficiency. When refrigeration power is included, net power reduction can be achieved when cooling efficiency exceeds $\sim$ 50% of Carnot limit. We present effective $V_{\mathrm{TH}}$ reduction methods for both nFET and pFET, critical for attaining high performance for cold CMOS.