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2020 IEEE Symposium on VLSI Technology最新文献

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Multi-Probe Characterization of Ferroelectric/Dielectric Interface by C-V, P-V and Conductance Methods 铁电/介电界面的C-V、P-V和电导多探针表征
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265069
Junkang Li, Y. Qu, M. Si, X. Lyu, P. Ye
{"title":"Multi-Probe Characterization of Ferroelectric/Dielectric Interface by C-V, P-V and Conductance Methods","authors":"Junkang Li, Y. Qu, M. Si, X. Lyu, P. Ye","doi":"10.1109/VLSITechnology18217.2020.9265069","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265069","url":null,"abstract":"In this work, we report on the multi-probe characterization of interfacial charges at the ferroelectric/dielectric (FE/DE) interface in response to both large-signal measurement associated with polarization switching and small-signal measurement without polarization switching. Charge densities at the FE/DE interface are extracted from temperature dependent C-V, P-V, conductance methods. It is found that the charge injection and accumulation at the FE/DE interface play a key role in the operation of FE/DE stack. These enormous trapped charges of 1013-1014 cm-2 at the FE/DE interface are supplied from the leakage current through the ultrathin DE layer. The proposed multi-probe measurement techniques provide a comprehensive understanding of FE/DE stack. The demonstrated leakage-assist polarization switching provides the new insights on the understanding of negative-capacitance (NC) effect and ferroelectric device performance.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75709444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS 三维集成硅光子/65nm CMOS的光采样ADC
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265101
N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović
{"title":"An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS","authors":"N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović","doi":"10.1109/VLSITechnology18217.2020.9265101","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265101","url":null,"abstract":"The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26 mathrm{fs}_{mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81558064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact Probabilistic Poisson Neuron based on Back-Hopping Oscillation in STT-MRAM for All-Spin Deep Spiking Neural Network 全自旋深脉冲神经网络STT-MRAM中基于回跳振荡的紧致概率泊松神经元
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265033
Ming-Hung Wu, Ming-Shun Huang, Zhifeng Zhu, Fu-Xiang Liang, Ming-Chun Hong, Jiefang Deng, Jeng-Hua Wei, S. Sheu, Chih-I Wu, G. Liang, T. Hou
{"title":"Compact Probabilistic Poisson Neuron based on Back-Hopping Oscillation in STT-MRAM for All-Spin Deep Spiking Neural Network","authors":"Ming-Hung Wu, Ming-Shun Huang, Zhifeng Zhu, Fu-Xiang Liang, Ming-Chun Hong, Jiefang Deng, Jeng-Hua Wei, S. Sheu, Chih-I Wu, G. Liang, T. Hou","doi":"10.1109/VLSITechnology18217.2020.9265033","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265033","url":null,"abstract":"A unique compact Poisson neuron that encodes information in the tunable duty cycle of probabilistic spike trains is presented as an enabling technology for cost-effective spiking neural network (SNN) hardware. The Poisson neuron exploits the back-hopping oscillation (BHO) in scalable spin-transfer torque (STT)-MRAM. The macrospin LLGS simulation confirms that the coupled local Joule heating and STT effects are responsible for the bias-dependent BHO. The complete neuron circuit design is at least $6times$ smaller than the state-of-the-art integrate-and- fire (IF) CMOS neuron. Hardware-friendly all-spin deep SNNs achieve equivalent accuracy to deep neural networks (DNN), 98.4 % for MNIST, even when considering the probabilistic nature of neurons.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86101343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window $( > 10mathrm{V})$ and Excellent 100K Endurance 具有大Vt存储窗口$(> 10 mathm {V})$和出色的100K续航力的超大尺寸半圆柱形(HC) 3D NAND器件
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265078
P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window $( > 10mathrm{V})$ and Excellent 100K Endurance","authors":"P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSITechnology18217.2020.9265078","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265078","url":null,"abstract":"We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area $(0.009mu mathrm{m}^{2}/mathrm{layer})$ is only ~ 32% of the standard GAA 3D NAND cell area, while it can produce very large $gt; 10mathrm{V}$ Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A “wake-up” effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, “hero” HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"64 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Immersion in Memory Compute (ImMC) Technology 沉浸式内存计算(ImMC)技术
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265019
C. T. Wang, W. L. Chang, C. Y. Chen, Douglas C. H. Yu
{"title":"Immersion in Memory Compute (ImMC) Technology","authors":"C. T. Wang, W. L. Chang, C. Y. Chen, Douglas C. H. Yu","doi":"10.1109/VLSITechnology18217.2020.9265019","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265019","url":null,"abstract":"Immersion in Memory Compute (ImMC) technology with multiple chips and functions in multi-layer stacking integrated using System on Integrated Chips (SoIC™) technology is presented. The technology provides multiple compute and memory chips to interconnect each other to gain computing power and memory bandwidth. The interconnect parasitics, bandwidth density and power efficiency are analyzed using N7 light IO transceiver. The ImMC compared with 3DIC with bridge and with shared die, respectively, using $mu mathrm{bump}$ and TSV, is studied. The ImMC is 16x, 14x, and 224x better than the 3DIC with bridge in bump density, data rate, and bandwidth density. The transceiver power and size for the ImMC is only 1 % of those for the 3DIC.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86465040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Probing the evolution of electrically active defects in doped ferroelectric HfO2 during wake-up and fatigue 研究掺杂铁电HfO2在唤醒和疲劳过程中电活性缺陷的演变
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265098
U. Celano, Y.H. Chen, A. Minj, K. Banerjee, N. Ronchi, S. Mcmitchell, P. Van Marcke, P. Favia, T.-L. Wu, B. Kaczer, G. Van den bosch, J. van Houdt, P. van der Heide
{"title":"Probing the evolution of electrically active defects in doped ferroelectric HfO2 during wake-up and fatigue","authors":"U. Celano, Y.H. Chen, A. Minj, K. Banerjee, N. Ronchi, S. Mcmitchell, P. Van Marcke, P. Favia, T.-L. Wu, B. Kaczer, G. Van den bosch, J. van Houdt, P. van der Heide","doi":"10.1109/VLSITechnology18217.2020.9265098","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265098","url":null,"abstract":"We correlate the concentration and configuration of electrical defects in ferroelectric Si -doped HfO2 (FE- HfO2) with the electrical device performance during wake-up and fatigue regimes. To this end, we combine time-to-breakdown (TDDB), Kelvin probe force microscopy (KPFM), conductive atomic force microcopy (C-AFM) and Scalpel SPM, probing for the first time, the nanoscopic material variations as a function of device's field cycling behavior.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"65 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83955533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology 垂直2T NOR (V2T)架构为NOR闪存技术提供可扩展和低功耗解决方案
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265037
H. Lue, T. Hsu, T. Yeh, Wei-Chen Chen, C. Lo, Chiatze Huang, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology","authors":"H. Lue, T. Hsu, T. Yeh, Wei-Chen Chen, C. Lo, Chiatze Huang, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSITechnology18217.2020.9265037","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265037","url":null,"abstract":"NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low-power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high-K metal-gate (HK/MG) integration is developed to provide high-performance BE-MANOS charge-trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low-voltage read (~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM).","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79998408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Atomic-scale imaging of polarization switching in an (anti-)ferroelectric memory material: Zirconia (ZrO2) (反)铁电记忆材料氧化锆(ZrO2)极化开关的原子尺度成像
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265091
S. Lombardo, C. Nelson, K. Chae, S. Reyes-Lillo, M. Tian, N. Tasneem, Z. Wang, M. Hoffmann, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, K. Cho, A. Kummel, J. Kacher, A. Khan
{"title":"Atomic-scale imaging of polarization switching in an (anti-)ferroelectric memory material: Zirconia (ZrO2)","authors":"S. Lombardo, C. Nelson, K. Chae, S. Reyes-Lillo, M. Tian, N. Tasneem, Z. Wang, M. Hoffmann, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, K. Cho, A. Kummel, J. Kacher, A. Khan","doi":"10.1109/VLSITechnology18217.2020.9265091","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265091","url":null,"abstract":"Direct, atomic-scale visualization of polarization switching in a functional, polycrystalline, binary oxide via insitu high-resolution transmission electron microscopy (HRTEM) biasing is reported for the first time. Antiferroelectric (AFE) ZrO2 was used as the model system, which is important for commercial DRAMs and as emerging NVMs (through work-function engineering). We observed (1) clear shifting and coalescing of domains within a single grain, and (2) dramatic changes of the atomic arrangements and crystalline phases-both at voltages above the critical voltage measured for AFE switching. Similar synergistic in-situ structural-electrical characterization can pave the way to understand and engineer microscopic mechanisms for retention, fatigue, variability, sub-coercive switching and analog states in ferroelectric and AFE-based memory devices.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78626091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Beyond 5G & Technologies: A Cross-Domain Vision 超越5G与技术:跨领域视野
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265087
E. Mercier
{"title":"Beyond 5G & Technologies: A Cross-Domain Vision","authors":"E. Mercier","doi":"10.1109/VLSITechnology18217.2020.9265087","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265087","url":null,"abstract":"5G deployment is on-going and many challenges are arising. New Radio (NR) Frequency Range 2 (FR2) in the millimeter (mmW) frequency domain starts being considered. Wideband over extended spectrum is targeted, enlightening broadband capacity and even much higher throughput than current views. In addition, spatial coverage based on quite small short wavelength antenna-array beam-forming offers new use case scenarii. As a consequence, the induced bands to support are increasing as well as the complexity of Front-End Module (FEM). But for autonomy and economical attraction, massive deployment can only happen with energy efficiency improvement. This paper will propose optimization paths for mm W system architectures, and their actual implementation, PHY considerations, and associated technology advances, for an holistic approach of the entire communication chain, and will highlight some promising trends for the development of 5G and beyond transceivers.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82417801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors 无结和反转模式FDSOI晶体管全工作状态下漏极电流变异性的表征和建模
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265036
D. Bosch, J. Colinge, G. Ghibaudo, X. Garros, S. Barraud, J. Lacord, B. Sklénard, L. Brunet, P. Batude, C. Fenouillet-Béranger, J. Cluzel, R. Kies, J. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu
{"title":"All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors","authors":"D. Bosch, J. Colinge, G. Ghibaudo, X. Garros, S. Barraud, J. Lacord, B. Sklénard, L. Brunet, P. Batude, C. Fenouillet-Béranger, J. Cluzel, R. Kies, J. Hartmann, C. Vizioz, G. Audoit, F. Balestra, F. Andrieu","doi":"10.1109/VLSITechnology18217.2020.9265036","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265036","url":null,"abstract":"We evidence a unique feature of junctionless Fully-Depleted Silicon-On-Insulator (JL FDSOI) transistors: the presence of both bulk and accumulation conduction renders standard VT-variability studies incomplete. For JL transistors, we rather propose an original analysis of the (local and global) variability in all-operation-regimes, from subthreshold to accumulation. We evidence that the current variability around VT is highly sensitive to back-bias VB and film thickness $(mathrm{t}_{mathrm{si}})$ uniformity. We demonstrate experimentally for the first time up to 70% lower drain current (ID) local variability for Junctionless Accumulation Mode (JAM) vs. inversion mode (IM) at 1V gate voltage (V G), $mathrm{L}=18$ nm gate length and $mathrm{W}=20mathrm{nm}$ width. This is attributed to the impurity screening, lowering the impact of Random Dopant Fluctuations variability.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"25 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82845005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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