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2020 IEEE Symposium on VLSI Technology最新文献

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Amorphous IGZO TFTs featuring Extremely-Scaled Channel Thickness and 38 nm Channel Length: Achieving Record High $G_{m.max}$ of 125 $mu mathrm{S}/mumathrm{m}$ at VDS of 1 V and ION of 350 μA/μm 具有极尺度通道厚度和38纳米通道长度的非晶IGZO tft:实现创纪录的高$G_{m。max}$为125 $mu mathm {S}/mu mathm {m}$， VDS为1 V，离子为350 μA/μm
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265052
S. Samanta, Kaizhen Ran, Chen Sun, Chengkuan Wang, Aaron Voon-Yew Thean, X. Gong
{"title":"Amorphous IGZO TFTs featuring Extremely-Scaled Channel Thickness and 38 nm Channel Length: Achieving Record High $G_{m.max}$ of 125 $mu mathrm{S}/mumathrm{m}$ at VDS of 1 V and ION of 350 μA/μm","authors":"S. Samanta, Kaizhen Ran, Chen Sun, Chengkuan Wang, Aaron Voon-Yew Thean, X. Gong","doi":"10.1109/VLSITechnology18217.2020.9265052","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265052","url":null,"abstract":"We demonstrated amorphous indium-gallium-zinc-oxide thin film transistors (a- IGZO TFTs) with extremely scaled channel thickness <tex>$t_{a-IGZO}$</tex> of 3.6 nm, achieving low SS of74.4 mV/decade and the highest <tex>$mu_{eff}$</tex> of34 cm<inf>2</inf>/V·s at carrier density <tex>$N_{carrier}$</tex> of ~5 × 10<inf>12</inf> cm-2 for a-IGZO TFTs having sub-10 nm <tex>$t_{alpha-IGZO}$</tex>. We found that there is no obvious degradation of mobility as <tex>$t_{alpha-IGZO}$</tex> changes from 6 nm to 3.6 nm. By scaling down the channel length <tex>$L_{CH}$</tex> to 38 nm, the devices have shown the highest extrinsic transconductance <tex>$G_{m}$</tex> of 125 <tex>$mumathrm{S}/mumathrm{m}$</tex> l (at <tex>$V_{DS}$</tex> of 1 V) and the highest on-state current ION of 350 <tex>$mu mathrm{A}/mu mathrm{m}$</tex> at VGS-VT of3.0 Vand <tex>$V_{DS}$</tex> of 2.5 V for any kind of a-IGZO TFTs.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73017310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Atomic-scale imaging of polarization switching in an (anti-)ferroelectric memory material: Zirconia (ZrO2) (反)铁电记忆材料氧化锆(ZrO2)极化开关的原子尺度成像
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265091
S. Lombardo, C. Nelson, K. Chae, S. Reyes-Lillo, M. Tian, N. Tasneem, Z. Wang, M. Hoffmann, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, K. Cho, A. Kummel, J. Kacher, A. Khan
{"title":"Atomic-scale imaging of polarization switching in an (anti-)ferroelectric memory material: Zirconia (ZrO2)","authors":"S. Lombardo, C. Nelson, K. Chae, S. Reyes-Lillo, M. Tian, N. Tasneem, Z. Wang, M. Hoffmann, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, K. Cho, A. Kummel, J. Kacher, A. Khan","doi":"10.1109/VLSITechnology18217.2020.9265091","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265091","url":null,"abstract":"Direct, atomic-scale visualization of polarization switching in a functional, polycrystalline, binary oxide via insitu high-resolution transmission electron microscopy (HRTEM) biasing is reported for the first time. Antiferroelectric (AFE) ZrO2 was used as the model system, which is important for commercial DRAMs and as emerging NVMs (through work-function engineering). We observed (1) clear shifting and coalescing of domains within a single grain, and (2) dramatic changes of the atomic arrangements and crystalline phases-both at voltages above the critical voltage measured for AFE switching. Similar synergistic in-situ structural-electrical characterization can pave the way to understand and engineer microscopic mechanisms for retention, fatigue, variability, sub-coercive switching and analog states in ferroelectric and AFE-based memory devices.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78626091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS 三维集成硅光子/65nm CMOS的光采样ADC
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265101
N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović
{"title":"An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS","authors":"N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović","doi":"10.1109/VLSITechnology18217.2020.9265101","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265101","url":null,"abstract":"The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26 mathrm{fs}_{mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81558064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Beyond 5G & Technologies: A Cross-Domain Vision 超越5G与技术:跨领域视野
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265087
E. Mercier
{"title":"Beyond 5G & Technologies: A Cross-Domain Vision","authors":"E. Mercier","doi":"10.1109/VLSITechnology18217.2020.9265087","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265087","url":null,"abstract":"5G deployment is on-going and many challenges are arising. New Radio (NR) Frequency Range 2 (FR2) in the millimeter (mmW) frequency domain starts being considered. Wideband over extended spectrum is targeted, enlightening broadband capacity and even much higher throughput than current views. In addition, spatial coverage based on quite small short wavelength antenna-array beam-forming offers new use case scenarii. As a consequence, the induced bands to support are increasing as well as the complexity of Front-End Module (FEM). But for autonomy and economical attraction, massive deployment can only happen with energy efficiency improvement. This paper will propose optimization paths for mm W system architectures, and their actual implementation, PHY considerations, and associated technology advances, for an holistic approach of the entire communication chain, and will highlight some promising trends for the development of 5G and beyond transceivers.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82417801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window $( > 10mathrm{V})$ and Excellent 100K Endurance 具有大Vt存储窗口$(> 10 mathm {V})$和出色的100K续航力的超大尺寸半圆柱形(HC) 3D NAND器件
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265078
P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window $( > 10mathrm{V})$ and Excellent 100K Endurance","authors":"P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSITechnology18217.2020.9265078","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265078","url":null,"abstract":"We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area $(0.009mu mathrm{m}^{2}/mathrm{layer})$ is only ~ 32% of the standard GAA 3D NAND cell area, while it can produce very large $gt; 10mathrm{V}$ Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A “wake-up” effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, “hero” HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"64 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85820751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compact Probabilistic Poisson Neuron based on Back-Hopping Oscillation in STT-MRAM for All-Spin Deep Spiking Neural Network 全自旋深脉冲神经网络STT-MRAM中基于回跳振荡的紧致概率泊松神经元
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265033
Ming-Hung Wu, Ming-Shun Huang, Zhifeng Zhu, Fu-Xiang Liang, Ming-Chun Hong, Jiefang Deng, Jeng-Hua Wei, S. Sheu, Chih-I Wu, G. Liang, T. Hou
{"title":"Compact Probabilistic Poisson Neuron based on Back-Hopping Oscillation in STT-MRAM for All-Spin Deep Spiking Neural Network","authors":"Ming-Hung Wu, Ming-Shun Huang, Zhifeng Zhu, Fu-Xiang Liang, Ming-Chun Hong, Jiefang Deng, Jeng-Hua Wei, S. Sheu, Chih-I Wu, G. Liang, T. Hou","doi":"10.1109/VLSITechnology18217.2020.9265033","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265033","url":null,"abstract":"A unique compact Poisson neuron that encodes information in the tunable duty cycle of probabilistic spike trains is presented as an enabling technology for cost-effective spiking neural network (SNN) hardware. The Poisson neuron exploits the back-hopping oscillation (BHO) in scalable spin-transfer torque (STT)-MRAM. The macrospin LLGS simulation confirms that the coupled local Joule heating and STT effects are responsible for the bias-dependent BHO. The complete neuron circuit design is at least $6times$ smaller than the state-of-the-art integrate-and- fire (IF) CMOS neuron. Hardware-friendly all-spin deep SNNs achieve equivalent accuracy to deep neural networks (DNN), 98.4 % for MNIST, even when considering the probabilistic nature of neurons.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"32 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86101343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Silicon is Greener: Why Innovation in Circuits is Needed for Sustainability 硅更环保:为什么电路创新需要可持续发展
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265102
J. Lloyd, Niall Kearney, C. Lyden, Damien McCartney, David Robertson, Meabh Shine
{"title":"Silicon is Greener: Why Innovation in Circuits is Needed for Sustainability","authors":"J. Lloyd, Niall Kearney, C. Lyden, Damien McCartney, David Robertson, Meabh Shine","doi":"10.1109/VLSITechnology18217.2020.9265102","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265102","url":null,"abstract":"Sustainable development is one of the preeminent challenges facing humanity. The immediate and near-term identified challenge is carbon emissions, driven primarily from the energy sector. The integrated circuit industry has created an information and communications revolution which has transformed every sector of the economy from education to agriculture. Can the innovation and power of the industry transform sustainability? In this paper, we will show that by enabling electrification of the power sector (efficiency) and virtualization of physical processes (reducing energy demand), the integrated circuit industry will be a key enabler for solutions to sustainability issues.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89771915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node 超过7nm节点的CMOS技术实现多vt器件缩放
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265050
V. Chang, S.H. Wang, J. Lu, W. Wu, B. Wu, B. Hsu, K. Kwong, J. Yeh, C. Chang, C.H. Chen, C. O. Chui, M. Yeh, K.B. Huang, R. Chen, K.S. Chen, S. Wu
{"title":"Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node","authors":"V. Chang, S.H. Wang, J. Lu, W. Wu, B. Wu, B. Hsu, K. Kwong, J. Yeh, C. Chang, C.H. Chen, C. O. Chui, M. Yeh, K.B. Huang, R. Chen, K.S. Chen, S. Wu","doi":"10.1109/VLSITechnology18217.2020.9265050","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265050","url":null,"abstract":"For the first time, multiple-Vt (multi-Vt) device options with Vt range> 250 mV are achieved in standard cells at dimensions beyond 7nm technology node. To overcome the common scaling challenges of potential device options such as FinFET and gate all-around (GAA) nanosheet transistor - gate length and cell height scaling, key enablers are identified, including novel, thin, and conformal work function metal (WFM) with enhanced patterning efficiency, high-k (HK) engineering, and precise WFM patterning boundary control. This work enables design flexibility for advanced CMOS technology beyond 7nm node with critical differentiators.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87053039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology 垂直2T NOR (V2T)架构为NOR闪存技术提供可扩展和低功耗解决方案
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265037
H. Lue, T. Hsu, T. Yeh, Wei-Chen Chen, C. Lo, Chiatze Huang, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology","authors":"H. Lue, T. Hsu, T. Yeh, Wei-Chen Chen, C. Lo, Chiatze Huang, Guan-Ru Lee, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSITechnology18217.2020.9265037","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265037","url":null,"abstract":"NOR Flash has stopped scaling for many years. However, recently there are increasingly new demands of NOR Flash in various 5G and IoT applications or wearable devices that strongly require new technology advancement of NOR. In this work, we developed a new vertical 2T (V2T) NOR Flash architecture that provides not only scaling capability but also low-power solutions. We leveraged the process of standard 3D NAND to develop a vertical 2T NOR that produces even smaller cell size than conventional planar 1T NOR. Advanced high-K metal-gate (HK/MG) integration is developed to provide high-performance BE-MANOS charge-trapping device with excellent 1M endurance and retention reliability. The 2T NOR architecture provides low-voltage read (~1V) that is compatible with advanced CMOS circuits without charge pumping to save power. We also suggest future technology extensions of the V2T NOR by adopting the ferroelectric memory devices (FeFET) and the 3DIC chiplets integration to broaden the applications fields of NOR technology in embedded Flash and computing in memory (CIM).","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79998408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Flexible and Transparent BEOL Monolithic 3DIC Technology for Human Skin Adaptable Internet of Things Chips 灵活透明的BEOL单片3DIC人体皮肤适应性物联网芯片
2020 IEEE Symposium on VLSI Technology Pub Date : 2020-06-01 DOI: 10.1109/VLSITechnology18217.2020.9265079
M. Kao, Wei-Hsiang Chen, Po-Cheng Hou, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh
{"title":"Flexible and Transparent BEOL Monolithic 3DIC Technology for Human Skin Adaptable Internet of Things Chips","authors":"M. Kao, Wei-Hsiang Chen, Po-Cheng Hou, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh","doi":"10.1109/VLSITechnology18217.2020.9265079","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265079","url":null,"abstract":"For the first time, below 400°C-fabricated poly-Si MOSFETs and 6T -SRAM fabrication process was demonstrated on polyimide (PI) substrate for flexible and transparent monolithic 3DIC. Key enablers are 400–900 nm transparent laser-stop layer (LsL), laser-crystallized/CMP-thinned poly Si channel and pulse UV-laser S/D activation. These advanced low thermal budget fabrication technologies enable stackable polySi MOSFETs on flexible 6” -wafer-scale PI substrate with high device uniformity $(mathrm{V}_{mathrm{th}}$ ‘SS~16.2%/16.6%) and bending stability $(mathrm{V}_{mathrm{th}}/mathrm{SS}sim 4.2%/9.8%)$ after cycle-bending at radius of 10mm. Such CMOS compatible technologies envision flexible 3D heterogeneous integration of circuits/optical sensors for human-skin adaptable Internet of Things (IoT) chips.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"41 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84675569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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