N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović
{"title":"三维集成硅光子/65nm CMOS的光采样ADC","authors":"N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović","doi":"10.1109/VLSITechnology18217.2020.9265101","DOIUrl":null,"url":null,"abstract":"The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26\\ \\mathrm{fs}_{\\mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS\",\"authors\":\"N. Mehta, Z. Su, E. Timurdogan, J. Notaros, R. Wilcox, C. Poulton, C. Baiocco, Nicholas M. Fahrenkopf, S. Kruger, Tat Ngai, Yukta Timalsina, M. Watts, V. Stojanović\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265101\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26\\\\ \\\\mathrm{fs}_{\\\\mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"19 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265101\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS
The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26\ \mathrm{fs}_{\mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.
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