An Optically Sampled ADC in 3D Integrated Silicon-Photonics/65nm CMOS

Abstract

The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter $(< 26\ \mathrm{fs}_{\mathrm{rms}})$ optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.