P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu
{"title":"An Extremely Scaled Hemi-Cylindrical (HC) 3D NAND Device with Large Vt Memory Window $( > 10\\mathrm{V})$ and Excellent 100K Endurance","authors":"P. Du, H. Lue, T. Yeh, T. Hsu, Wei-Chen Chen, Chiatze Huang, Guan-Ru Lee, Min-Feng Hung, C. Chiu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSITechnology18217.2020.9265078","DOIUrl":null,"url":null,"abstract":"We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area $(0.009\\mu \\mathrm{m}^{2}/\\mathrm{layer})$ is only ~ 32% of the standard GAA 3D NAND cell area, while it can produce very large $gt; 10\\mathrm{V}$ Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A “wake-up” effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, “hero” HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"64 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265078","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We report an extremely scaled HC 3D NAND device with large memory window in this paper. The proposed cell area $(0.009\mu \mathrm{m}^{2}/\mathrm{layer})$ is only ~ 32% of the standard GAA 3D NAND cell area, while it can produce very large $gt; 10\mathrm{V}$ Vt memory window with excellent 100K endurance. We also study the size effect of HC device. It is found that the larger (taller) HC device may easily suffer parasitic edge leakage effect that causes programming saturation issue. A “wake-up” effect by an initial strong -FN erasing can introduce gate injected electrons that electrically suppress the parasitic edge and in turn “wake-up” the device to produce larger programming window. On the other hand, the smaller HC device already shows excellent memory window without the need of wake-up. Good post-cycled retention and RTN performance are demonstrated for an extremely scaled, “hero” HC device. Our results suggest a promising path of 3D NAND device to enjoy both aggressive dimension scaling and large memory window.