H. Cheng, I. Kuo, W. Chien, C. Yeh, Y. Chou, N. Gong, L. Gignac, C. Yang, C. Cheng, C. Lavoie, M. Hopstaken, R. Bruce, L. Buzi, E. Lai, F. Carta, A. Ray, M. Lee, H. Ho, W. Kim, M. BrightSky, H. Lung
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Si Incorporation Into AsSeGe Chalcogenides for High Thermal Stability, High Endurance and Extremely Low $\mathrm{V}_{\mathrm{th}}$ Drift 3D Stackable Cross-point Memory : IBM/Macronix PCRAM Joint Project
By incorporating Si into AsSeGe system, we demonstrate a 3D stackable OTS+PCM memory in a 1k by 1k cross-point memory array with extremely low $\mathrm{V}_{\mathrm{tS}}$ drift (~0V after 3 days from programming), wide $\mathrm{V}_{\mathrm{tS}}/\mathrm{V}_{\mathrm{tR}}$ window (>2V main distribution memory window), high endurance (>2E11 cycles), excellent $\mathrm{I}_{\mathrm{OFF}}$ and thermal stability. So far, attempts to improve the thermal stability of AsSeGe system sacrifice $\mathrm{I}_{\mathrm{OFF}}$ and cycling endurance. We show that Si incorporation relaxes this trade-off and can greatly improve the thermal stability and cycling endurance while also achieving good $\mathrm{I}_{\mathrm{OFF}}$. In particular the $\mathrm{I}_{\mathrm{OFF}}$ of AsSeGeSi selector is improved over the AsSeGe system for films of 20 nm.