K. Cheng, Chanro Park, Heng Wu, Juntao Li, S. Nguyen, Jingyun Zhang, Miaomiao Wang, S. Mehta, Zuoguang Liu, R. Conti, N. Loubet, J. Frougier, A. Greene, T. Yamashita, B. Haran, R. Divakaruni
{"title":"基于自对准触点(SAC)和主动栅极触点(COAG)的高尺度CMOS技术改进空气间隔器","authors":"K. Cheng, Chanro Park, Heng Wu, Juntao Li, S. Nguyen, Jingyun Zhang, Miaomiao Wang, S. Mehta, Zuoguang Liu, R. Conti, N. Loubet, J. Frougier, A. Greene, T. Yamashita, B. Haran, R. Divakaruni","doi":"10.1109/VLSITechnology18217.2020.9265096","DOIUrl":null,"url":null,"abstract":"We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{\\mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1984 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology\",\"authors\":\"K. Cheng, Chanro Park, Heng Wu, Juntao Li, S. Nguyen, Jingyun Zhang, Miaomiao Wang, S. Mehta, Zuoguang Liu, R. Conti, N. Loubet, J. Frougier, A. Greene, T. Yamashita, B. Haran, R. Divakaruni\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265096\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{\\\\mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"1984 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265096\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265096","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact Over Active Gate (COAG) for Highly Scaled CMOS Technology
We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{\mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.