A. Pal, J. Ferrell, A. Sachid, E. Bazizi, D. Cui, A. Wang, M. Cogorno, A. Bhatnagar, N. Ingle, Y. Xu, W. Lei, Y. Lei, A. Gelatos, T. Ha, K. Kashefizadeh, S. Seutter, T. Sato, B. Brown, K. Mikhaylichenko, C. Lee, N. Fung, W. Xu, M. Kawasaki, T. Luu, P. Wang, B. Colombeau, B. Alexander, D. Hwang, S. Natarajan, B. Ayyagari
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引用次数: 0
Abstract
Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.
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