S. Salahuddin, M. Perumkunnil, E. Litta, A. Gupta, P. Weckx, J. Ryckaert, M. Na, A. Spessot
{"title":"N3中埋电SRAM DTCO和系统级基准测试","authors":"S. Salahuddin, M. Perumkunnil, E. Litta, A. Gupta, P. Weckx, J. Ryckaert, M. Na, A. Spessot","doi":"10.1109/VLSITechnology18217.2020.9265076","DOIUrl":null,"url":null,"abstract":"The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as SRAM performance and write ability booster in 3nm node. BPR-SRAM offers up to 34.5% read speed and 498.6mV write margin improvement over conventional SRAM. Gem5 system simulator predicts up to 28.2% performance gain with server-processor having BPR-SRAM in L2 and L3 cache as compared to the baseline.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"20 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Buried power SRAM DTCO and system-level benchmarking in N3\",\"authors\":\"S. Salahuddin, M. Perumkunnil, E. Litta, A. Gupta, P. Weckx, J. Ryckaert, M. Na, A. Spessot\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265076\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as SRAM performance and write ability booster in 3nm node. BPR-SRAM offers up to 34.5% read speed and 498.6mV write margin improvement over conventional SRAM. Gem5 system simulator predicts up to 28.2% performance gain with server-processor having BPR-SRAM in L2 and L3 cache as compared to the baseline.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"20 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265076\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Buried power SRAM DTCO and system-level benchmarking in N3
The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as SRAM performance and write ability booster in 3nm node. BPR-SRAM offers up to 34.5% read speed and 498.6mV write margin improvement over conventional SRAM. Gem5 system simulator predicts up to 28.2% performance gain with server-processor having BPR-SRAM in L2 and L3 cache as compared to the baseline.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
