Soyoun Kim, S. Kim, Taiko Yamaguchi, Jae Chul Kim, Byung-Gook Park, Y. Y. Masuoka, S. Kwon
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Local Variation-Aware Transistor Design through Comprehensive Analysis of Various Vdd/Temperatures Using Sub- 7nm Advanced FinFET Technology
In this paper, key contributors to local variability of sub-7nm FinFET has been identified in various operating environments. Through a comprehensive analysis, different root-cause for high and low temperature region have been revealed and confirmed by advanced Si wafer for the first time. Moreover, a local variation-aware transistor was successfully demonstrated to reduce $\sigma V_{\mathrm{min}}$ distribution by 0.5 x and 0.3 x at cold temperature.
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