Record Low Contact Resistivity to Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ and GeSn:B $(4.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ with Optimized [B] and [Sn] by In-situ CVD Doping
Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, C. Liu
{"title":"Record Low Contact Resistivity to Ge:B $(8.1\\mathrm{x}10^{-10}\\Omega-\\mathrm{cm}^{2})$ and GeSn:B $(4.1\\mathrm{x}10^{-10}\\Omega-\\mathrm{cm}^{2})$ with Optimized [B] and [Sn] by In-situ CVD Doping","authors":"Fang-Liang Lu, Yi-Chun Liu, Chung-En Tsai, Hung-Yu Ye, C. Liu","doi":"10.1109/VLSITechnology18217.2020.9265009","DOIUrl":null,"url":null,"abstract":"The record low contact resistivity <tex>$(\\rho_{\\mathrm{c}})$</tex> of Ti contact to Ge:B <tex>$(8.1\\mathrm{x}10^{-10}\\Omega-\\mathrm{cm}^{2})$</tex> is achieved by in-situ doped CVD using the high-order Ge precursor <tex>$(\\mathrm{Ge}_{2}\\mathrm{H}_{6})$</tex>. The best achievable <tex>$[\\mathrm{B}]_{\\mathrm{act}}$</tex>. of <tex>$7\\mathrm{x}10^{20}\\mathrm{cm}^{-3}$</tex> and extended epitaxial process window are obtained using <tex>$\\mathrm{Ge}_{2}\\mathrm{H}_{6}$</tex>. By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest <tex>$\\mathrm{p}_{\\mathrm{c}}$</tex> of <tex>$4.1\\mathrm{x}10^{-10} \\Omega-\\mathrm{cm}^{2}$</tex>. Further Sn addition (4.7% and 13.2%) increases <tex>$\\rho_{\\mathrm{c}}$</tex> due to reduced [B], and degrades the thermal stability. The record low resistivity <tex>$(2\\mathrm{x}10^{-4}\\Omega-\\mathrm{cm})$</tex> among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes (<tex>$\\mathrm{Cl}_{2}+\\mathrm{BCl}_{3}$</tex> for metal on <tex>$\\mathrm{GeSn}:\\mathrm{B}$</tex>, while <tex>$\\mathrm{C}1_{2}$</tex> for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the <tex>$\\rho_{\\mathrm{c}}$</tex>. B segregation <tex>$(> 1\\mathrm{x}10^{21}\\mathrm{cm}^{-3})$</tex> at the metal/semiconductor interface enables the record low <tex>$\\rho_{\\mathrm{c}}$</tex>.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"35 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265009","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The record low contact resistivity $(\rho_{\mathrm{c}})$ of Ti contact to Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ is achieved by in-situ doped CVD using the high-order Ge precursor $(\mathrm{Ge}_{2}\mathrm{H}_{6})$. The best achievable $[\mathrm{B}]_{\mathrm{act}}$. of $7\mathrm{x}10^{20}\mathrm{cm}^{-3}$ and extended epitaxial process window are obtained using $\mathrm{Ge}_{2}\mathrm{H}_{6}$. By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest $\mathrm{p}_{\mathrm{c}}$ of $4.1\mathrm{x}10^{-10} \Omega-\mathrm{cm}^{2}$. Further Sn addition (4.7% and 13.2%) increases $\rho_{\mathrm{c}}$ due to reduced [B], and degrades the thermal stability. The record low resistivity $(2\mathrm{x}10^{-4}\Omega-\mathrm{cm})$ among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes ($\mathrm{Cl}_{2}+\mathrm{BCl}_{3}$ for metal on $\mathrm{GeSn}:\mathrm{B}$, while $\mathrm{C}1_{2}$ for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the $\rho_{\mathrm{c}}$. B segregation $(> 1\mathrm{x}10^{21}\mathrm{cm}^{-3})$ at the metal/semiconductor interface enables the record low $\rho_{\mathrm{c}}$.
利用高阶Ge前驱体$(\mathrm{Ge}_{2}\mathrm{H}_{6})$原位掺杂CVD,实现了Ti与Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$接触的低接触电阻率$(\rho_{\mathrm{c}})$。最好的可以实现$[\mathrm{B}]_{\mathrm{act}}$。利用$\mathrm{Ge}_{2}\mathrm{H}_{6}$得到了$7\mathrm{x}10^{20}\mathrm{cm}^{-3}$和扩展的外延工艺窗口。通过优化[B]和[Sn], 2% Sn addition into Ge epitaxy reaches the lowest $\mathrm{p}_{\mathrm{c}}$ of $4.1\mathrm{x}10^{-10} \Omega-\mathrm{cm}^{2}$. Further Sn addition (4.7% and 13.2%) increases $\rho_{\mathrm{c}}$ due to reduced [B], and degrades the thermal stability. The record low resistivity $(2\mathrm{x}10^{-4}\Omega-\mathrm{cm})$ among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes ($\mathrm{Cl}_{2}+\mathrm{BCl}_{3}$ for metal on $\mathrm{GeSn}:\mathrm{B}$, while $\mathrm{C}1_{2}$ for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the $\rho_{\mathrm{c}}$. B segregation $(> 1\mathrm{x}10^{21}\mathrm{cm}^{-3})$ at the metal/semiconductor interface enables the record low $\rho_{\mathrm{c}}$.