GaN and Si Transistors on 300mm Si(111) enabled by 3D Monolithic Heterogeneous Integration

We expand on our work in [1] by demonstrating both Si P- and NMOS finfet transistors monolithically integrated with GaN transistors on 300mm Si(111) wafers using 3D integration. With the Si finfet architecture, we are able to take advantage of the fin orientations of the transferred Si(100) crystal to fabricate both high performance Si P- and NMOS transistors. Furthermore, we demonstrate a variety of GaN transistor innovations, including enhancement (e-mode) and depletion mode (d-mode) GaN NMOS transistor with high $\mathrm{I}_{\mathrm{D}}=1.8\mathrm{m}_{1}\mathrm{W}\mu \mathrm{m};\mathrm{GaN}$ Schottky gate transistor producing high saturated power of 20dBm with peak PAE=57% at 28GHz; high performing, low leakage cascode and multi-gate GaN transistors; and GaN Schottky diodes with ultra-low $\mathrm{C}_{\mathrm{OFF}}$ for ESD protection, all integrated on 300mm Si(111) wafer.