Ultrahigh responsivity and tunable photogain BEOL compatible $\mathrm{MoS}_{2}$ phototransistor array for monolithic 3D image sensor with block-level sensing circuits
Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee
{"title":"Ultrahigh responsivity and tunable photogain BEOL compatible $\\mathrm{MoS}_{2}$ phototransistor array for monolithic 3D image sensor with block-level sensing circuits","authors":"Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee","doi":"10.1109/VLSITechnology18217.2020.9265017","DOIUrl":null,"url":null,"abstract":"A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\\ \\mathrm{A}/\\mathrm{W})$ and tunable photogain (102~105) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (102~105) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.