Ultrahigh responsivity and tunable photogain BEOL compatible $\mathrm{MoS}_{2}$ phototransistor array for monolithic 3D image sensor with block-level sensing circuits

Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee
{"title":"Ultrahigh responsivity and tunable photogain BEOL compatible $\\mathrm{MoS}_{2}$ phototransistor array for monolithic 3D image sensor with block-level sensing circuits","authors":"Chih-Chao Yang, Ping-Yi Hsieh, Po-Han Chen, Tung-Ying Hsieh, Po-Tsang Huang, Yu-Ting Lin, C. Shen, J. Shieh, Da-Chiang Chang, W. Yeh, Meng-Chyi Wu, Yi‐Hsien Lee","doi":"10.1109/VLSITechnology18217.2020.9265017","DOIUrl":null,"url":null,"abstract":"A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\\ \\mathrm{A}/\\mathrm{W})$ and tunable photogain (102~105) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (102~105) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.
用于具有块级传感电路的单片3D图像传感器的超高响应性和可调光增益BEOL兼容的$\mathrm{MoS}_{2}$光电晶体管阵列
在单片三维图像传感器方案中采用大面积可扩展单层TMD是可行的。我们首次提出了一个具有超高响应性$(> 10^{3}\ \ mathm {a}/\ mathm {W})$和可调谐光增益(102~105)的$\ mathm {MoS}_{2}$光电晶体管阵列原型,该阵列可直接实现在与BEOL细间距垂直互连连接的CMOS电路上。电门脉冲调制减轻了层状半导体界面的光门控(PG)和持续光导(PPC)效应。三个数量级的响应速度改进和细间距垂直互连增强了块级压缩感知电路和全局图像信号处理,以实现增益控制和数据压缩。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信