V. B. Naik, K. Yamane, J. H. Lim, T. Y. Lee, J. Kwon, Behin Aein, N. Chung, L. Y. Hau, R. Chao, D. Zeng, Y. Otani, C. Chiang, Y. Huang, L. Pu, N. Thiyagarajah, S. Jang, W. Neo, H. Dixit, S.-K., L. C. Goh, T. Ling, J. Hwang, J. W. Ting, L. Zhang, R. Low, N. Balasankaran, C. Seet, S. Ong, J. Wong, Y. You, S. Woo, S. Siah
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A Reliable TDDB Lifetime Projection Model Verified Using 40Mb STT-MRAM Macro at Sub-ppm Failure Rate To Realize Unlimited Endurance for Cache Applications
We report a reliable TDDB lifetime projection model using power law verified from 40Mb STT-MRAM macro at sub-ppm failure rate to realize nearly unlimited endurance for cache applications. A specially designed macro, having internal temperature control systems and capable of applying accelerated voltage at 40Mb array level with wide operating temperature range: −40~125 °C and varying pulse widths: 200~10 ns, is used for the study. We demonstrate a superior endurance performance of > 1 E 12 cycles at 1 ppm failure rate using 40Mb macro combined with SRAM -like MTJ stack with lower operating voltage at BER ~ 1 ppm at 1 0 ns write pulse.
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