J. Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shute, Fumitaka Sugaya, M. Materano, T. Ali, Kati Kuehnel, Konrad Seide, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi
{"title":"基于铁电f0.5 zr0.5 o2的SoC兼容1t1 C FeRAM存储阵列","authors":"J. Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shute, Fumitaka Sugaya, M. Materano, T. Ali, Kati Kuehnel, Konrad Seide, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi","doi":"10.1109/VLSITechnology18217.2020.9265063","DOIUrl":null,"url":null,"abstract":"This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $\\mathrm{Hf}_{0.5}\\mathrm{Zr}_{0.5}\\mathrm{O}_{2}(\\mathrm{HZO}$)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2\\mathrm{P}_{\\mathrm{r}} > 4\\vert \\mu\\mathrm{C}/\\mathrm{cm}^{2}$, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"28 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2\",\"authors\":\"J. Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shute, Fumitaka Sugaya, M. Materano, T. Ali, Kati Kuehnel, Konrad Seide, U. Schroeder, T. Mikolajick, M. Tsukamoto, T. Umebayashi\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265063\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $\\\\mathrm{Hf}_{0.5}\\\\mathrm{Zr}_{0.5}\\\\mathrm{O}_{2}(\\\\mathrm{HZO}$)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2\\\\mathrm{P}_{\\\\mathrm{r}} > 4\\\\vert \\\\mu\\\\mathrm{C}/\\\\mathrm{cm}^{2}$, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"28 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265063\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SoC compatible 1 T1 C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2
This paper experimentally demonstrates fundamental memory array operation of a ferroelectric HfO2-based 1 T1 C FeRAM. Metal/ferroelectric/metal (MFM) capacitors consisting of a TiN/ $\mathrm{Hf}_{0.5}\mathrm{Zr}_{0.5}\mathrm{O}_{2}(\mathrm{HZO}$)/TiN stack were optimized for a sub 500°C process. Structures revealed excellent performance such as remanent polarization $2\mathrm{P}_{\mathrm{r}} > 4\vert \mu\mathrm{C}/\mathrm{cm}^{2}$, endurance> 1011 cycles, and 10 years data retention at 85°C. Furthermore, the MFM capacitors were successfully integrated into a 64 kbit 1T1C FeRAM array including our dedicated circuit for array operation. Back-end-of-line (BEOL) wiring showed no degradation of the underlying CMOS logic. Program and read operation were properly controlled resulting in 100 % bit functionality at an operation voltage of2.5 Vand operating speed at 14 ns. This technology matches requirements of last level cash (LLC) and embedded non-volatile-memory (NVM) in low power System-on-a-Chip (SoC) for IoT applications.