C. Cavalcante, C. Fenouillet-Beranzer, P. Batude, X. Garros, X. Federspiel, J. Lacord, S. Kerdilès, A. Royet, P. Acosta-Alba, O. Rozeau, V. Barral, F. Arnaud, N. Planes, P. Sassoulas, E. Ghegin, R. Beneyton, M. Grégoire, O. Weber, C. Guérin, L. Arnaud, S. Moreau, R. Kies, G. Romano, N. Rambal, A. Magalhaes, G. Ghibaudo, J-P. Colinag, M. Vinet, F. Andrieu
{"title":"28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis","authors":"C. Cavalcante, C. Fenouillet-Beranzer, P. Batude, X. Garros, X. Federspiel, J. Lacord, S. Kerdilès, A. Royet, P. Acosta-Alba, O. Rozeau, V. Barral, F. Arnaud, N. Planes, P. Sassoulas, E. Ghegin, R. Beneyton, M. Grégoire, O. Weber, C. Guérin, L. Arnaud, S. Moreau, R. Kies, G. Romano, N. Rambal, A. Magalhaes, G. Ghibaudo, J-P. Colinag, M. Vinet, F. Andrieu","doi":"10.1109/VLSITechnology18217.2020.9265075","DOIUrl":null,"url":null,"abstract":"For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It is shown that 500°C 2h thermal budget can be applied on a digital 28nm circuit including State-Of- The-Art Cu/ULK BEOL without yield nor reliability degradation. These results pave the way to the introduction of BEOL between tiers in 3D sequential integration while the thermal budget allowed for the top tier is sufficient to lead to high performance device.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It is shown that 500°C 2h thermal budget can be applied on a digital 28nm circuit including State-Of- The-Art Cu/ULK BEOL without yield nor reliability degradation. These results pave the way to the introduction of BEOL between tiers in 3D sequential integration while the thermal budget allowed for the top tier is sufficient to lead to high performance device.
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