N. Gong, W. Chien, Y. Chou, C. Yeh, N. Li, H. Cheng, C. Cheng, I. Kuo, C. Yang, R. Bruce, A. Ray, L. Gignac, Y. Lin, C. Miller, T. Perri, W. Kim, L. Buzi, H. Utomo, F. Carta, E. Lai, H. Ho, H. Lung, M. BrightSky
{"title":"A no-verification Multi-Level-Cell (MLC) operation in Cross-Point OTS-PCM : IBM/Macronix Phase Change Memory Joint Project","authors":"N. Gong, W. Chien, Y. Chou, C. Yeh, N. Li, H. Cheng, C. Cheng, I. Kuo, C. Yang, R. Bruce, A. Ray, L. Gignac, Y. Lin, C. Miller, T. Perri, W. Kim, L. Buzi, H. Utomo, F. Carta, E. Lai, H. Ho, H. Lung, M. BrightSky","doi":"10.1109/VLSITechnology18217.2020.9265020","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265020","url":null,"abstract":"We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (> 109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under “1/2V” scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"49 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73603831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dongjae Shin, H. Byun, Dongshik Shim, J. Cha, Yonghwack Shin, C. Shin, Chang-Bum Lee, Eunkyung Lee, Bongyong Jang, Jisan Lee, Inoh Hwang, Jinmyoung Kim, Kyunghyun Son, K. Ha, H. Choo
{"title":"III/V-on-bulk-Si technology for commercially viable photonics-integrated VLSI","authors":"Dongjae Shin, H. Byun, Dongshik Shim, J. Cha, Yonghwack Shin, C. Shin, Chang-Bum Lee, Eunkyung Lee, Bongyong Jang, Jisan Lee, Inoh Hwang, Jinmyoung Kim, Kyunghyun Son, K. Ha, H. Choo","doi":"10.1109/VLSITechnology18217.2020.9265088","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265088","url":null,"abstract":"We have demonstrated a complete set of on-chip Si-photonic components using our III/V-on-bulk-silicon (Si) technology. Our bulk-Si-based technology shows unrivaled CMOS compatibility and much improved thermal dissipation, leading to superior performance over the III/V-on-SOI technology at a fraction of cost. The components demonstrated on the bulk-Si platform include single & tunable wavelength laser diodes, semiconductor optical amplifiers, Ge & III/V photodiodes, modulators, waveguides, and couplers. Fabrication of Si-photonics components are all carried out on the same bulk wafers that will host CMOS ICs, and all the fabricated components show robust performance in experimental characterizations. Using these bulk-Si components, a solid-state beam scanner for the light detection and ranging (LiDAR) system is currently under development. The III/V-on-bulk-Si technology will open a new path for silicon photonics to share and enjoy the colossal infrastructure and remarkable commercial success of the CMOS technology in coming years.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80042906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Subramanian, M. Hosseini, T. Chiarella, S. Sarkar, P. Schuddinck, B. Chan, D. Radisic, G. Mannaert, A. Hikavyy, E. Rosseel, F. Sebaai, A. Peter, T. Hopf, P. Morin, S. Wang, K. Devriendt, D. Batuk, G. Martinez, A. Veloso, E. Litta, S. Baudot, Y. Siew, X. Zhou, B. Briggs, E. Capogreco, J. Hung, R. Koret, A. Spessot, J. Ryckaert, S. Demuynck, N. Horiguchi, J. Boemmels
{"title":"First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers","authors":"S. Subramanian, M. Hosseini, T. Chiarella, S. Sarkar, P. Schuddinck, B. Chan, D. Radisic, G. Mannaert, A. Hikavyy, E. Rosseel, F. Sebaai, A. Peter, T. Hopf, P. Morin, S. Wang, K. Devriendt, D. Batuk, G. Martinez, A. Veloso, E. Litta, S. Baudot, Y. Siew, X. Zhou, B. Briggs, E. Capogreco, J. Hung, R. Koret, A. Spessot, J. Ryckaert, S. Demuynck, N. Horiguchi, J. Boemmels","doi":"10.1109/VLSITechnology18217.2020.9265073","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265073","url":null,"abstract":"We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85361200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recent progresses in STT-MRAM and SOT-MRAM for next generation MRAM","authors":"T. Endoh, H. Honjo, K. Nishioka, S. Ikeda","doi":"10.1109/VLSITechnology18217.2020.9265042","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265042","url":null,"abstract":"In last decade, since high performance MTJ using CoFeB/MgO-based interfacial perpendicular magnetic anisotropy (IPMA) is utilized, STT-MRAM technology has rapidly progressed and mass-production of STT-MRAM has already started in the semiconductor companies. However, for further expansion of MRAM applications and markets, higher reliability, larger capacity or speed are required. In this invited paper, we describe our recent progresses in STT-/SOT-MRAM fabricated under developed 300mm integration process (PVD, RIE etc.) [4] with advanced spintronics device technologies, such as quad-interface MTJ [10] and canted SOT device [12].","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"18 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86023446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shan Deng, Guodong Yin, W. Chakraborty, S. Dutta, S. Datta, Xueqing Li, K. Ni
{"title":"A Comprehensive Model for Ferroelectric FET Capturing the Key Behaviors: Scalability, Variation, Stochasticity, and Accumulation","authors":"Shan Deng, Guodong Yin, W. Chakraborty, S. Dutta, S. Datta, Xueqing Li, K. Ni","doi":"10.1109/VLSITechnology18217.2020.9265014","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265014","url":null,"abstract":"In this work, we developed a comprehensive model for ferroelectric FET (FeFET), which can capture all the essential ferroelectric behaviors. Unlike previous models, which can describe only a subset but not all the reported ferroelectric behaviors, the proposed model can: i) predict device performance with geometry scaling; ii) quantify the device-to-device variation with device scaling; iii) exhibit stochasticity during a single domain switching; and iv) capture the accumulation of domain switching probability with applied pulse trains. This comprehensive model would enable researchers to explore a wide range of FeFET applications and guide device development, optimization and benchmarking.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"23 5 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91135065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Sato, G. Allen, William P. Benson, B. Buford, Atreyee Chakraborty, M. Christenson, T. Gosavi, P. Heil, N. Kabir, B. Krist, K. O’Brien, K. Oguz, Rohan Patil, J. Pellegren, A. Smith, E. S. Walker, P. Hentges, M. Metz, M. Seth, B. Turkot, C. Wiegand, H. Yoo, I. Young
{"title":"CMOS Compatible Process Integration of SOT-MRAM with Heavy-Metal Bi-Layer Bottom Electrode and 10ns Field-Free SOT Switching with STT Assist","authors":"N. Sato, G. Allen, William P. Benson, B. Buford, Atreyee Chakraborty, M. Christenson, T. Gosavi, P. Heil, N. Kabir, B. Krist, K. O’Brien, K. Oguz, Rohan Patil, J. Pellegren, A. Smith, E. S. Walker, P. Hentges, M. Metz, M. Seth, B. Turkot, C. Wiegand, H. Yoo, I. Young","doi":"10.1109/VLSITechnology18217.2020.9265028","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265028","url":null,"abstract":"This paper demonstrates a CMOS compatible process integration of spin-orbit torque (SOT) device with a unique bilayer SOT bottom electrode. An effective spin-Hall angle of 0.27, a median tunneling magneto-resistance ratio of 127% at electrical CD of 57 nm, and a 96% resistance-based MTJ yield on 300 mm scale were achieved. We experimentally validated the two-pulse field-free SOT switching scheme with spin-transfer torque assist at 10ns. Unlike conventional field-free SOT switching schemes, the demonstrated scheme adds no complexity to process integration.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80427057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Srimani, G. Hills, M. Bishop, C. Lau, P. Kanhaiya, R. Ho, A. Amer, M. Chao, A. Yu, A. Wright, A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, G. Clark, G. Michaelson, M. Johnson, K. Kelley, P. Manos, K. Mi, U. Suriono, S. Vuntangboon, H. Xue, J. Humes, S. Soares, B. Jones, S. Burack, Arvind, A. Chandrakasan, B. Ferguson, M. Nelson, M. Shulaker
{"title":"Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node","authors":"T. Srimani, G. Hills, M. Bishop, C. Lau, P. Kanhaiya, R. Ho, A. Amer, M. Chao, A. Yu, A. Wright, A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, G. Clark, G. Michaelson, M. Johnson, K. Kelley, P. Manos, K. Mi, U. Suriono, S. Vuntangboon, H. Xue, J. Humes, S. Soares, B. Jones, S. Burack, Arvind, A. Chandrakasan, B. Ferguson, M. Nelson, M. Shulaker","doi":"10.1109/VLSITechnology18217.2020.9265083","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265083","url":null,"abstract":"The inevitable slowing of two-dimensional scaling is motivating efforts to continue scaling along a new physical axis: the 3rd dimension. Here we report back-end-of-line (BEOL) integration of multi-tier logic and memory established within a commercial foundry. This is enabled by a low-temperature BEOL-compatible complementary carbon nanotube (CNT) field-effect transistor (CNFET) logic technology, alongside a BEOL-compatible Resistive RAM (RRAM) technology. All vertical layers are fabricated sequentially over the same starting substrate, using conventional BEOL nano-scale inter-layer vias (ILVs) as vertical interconnects (e.g., monolithic 3D integration, rather than chip-stacking and bonding). In addition, we develop the entire VLSI design infrastructure required for a foundry technology offering, including an industry-practice monolithic 3D process design kit (PDK) as well as a complete monolithic 3D standard cell library. The initial foundry process integrates 4 device tiers (2 tiers of complementary CNFET logic and 2 tiers of RRAM memory) with 15 metal layers at a ~130 nm technology node. We fabricate and experimentally validate the standard cell library across all monolithic 3D tiers, as well as a range of sub-systems including memories (BEOL SRAM, 1T1R memory arrays) as well as logic (including the compute core of a 16-bit microprocessor) - all of which is fabricated in the foundry within the BEOL interconnect stack. All fabrication is VLSI-compatible and leverages existing silicon CMOS infrastructure, and the entire design flow is compatible with existing commercial electronic design automation tools.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"121 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76731894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Demin Liu, Po-Chih Chen, C. Hsiung, Shin-Yi Huang, Yan-Pin Huang, S. Verhaverbeke, G. Mori, Kuan-Neng Chen
{"title":"Low Temperature Cu/SiO2 Hybrid Bonding with Metal Passivation","authors":"Demin Liu, Po-Chih Chen, C. Hsiung, Shin-Yi Huang, Yan-Pin Huang, S. Verhaverbeke, G. Mori, Kuan-Neng Chen","doi":"10.1109/VLSITechnology18217.2020.9265008","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265008","url":null,"abstract":"Cu/SiO2 hybrid bonding process with short duration (1 minute) has been successfully performed at low temperature (120°C) under the atmosphere with metal passivation material. Electrical performance (over 15K daisy chain and $10^{-8}Omega-mathrm{cm}^{2}$ specific contact resistance), mechanical strength $(> 15mathrm{kgf})$, and reliability have been conducted to verify its excellent bonding quality. This method of hybrid bonding therefore provides a wide range of applications and a new solution for 3D integration.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79241798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Doevenspeck, K. Garello, B. Verhoef, R. Degraeve, S. Van Beek, D. Crotti, F. Yasin, S. Couet, G. Jayakumar, I. Papistas, P. Debacker, R. Lauwereins, W. Dehaene, G. Kar, S. Cosemans, A. Mallik, D. Verkest
{"title":"SOT-MRAM based Analog in-Memory Computing for DNN inference","authors":"J. Doevenspeck, K. Garello, B. Verhoef, R. Degraeve, S. Van Beek, D. Crotti, F. Yasin, S. Couet, G. Jayakumar, I. Papistas, P. Debacker, R. Lauwereins, W. Dehaene, G. Kar, S. Cosemans, A. Mallik, D. Verkest","doi":"10.1109/VLSITechnology18217.2020.9265099","DOIUrl":"https://doi.org/10.1109/VLSITechnology18217.2020.9265099","url":null,"abstract":"Deep neural network (DNN) inference requires a massive amount of matrix-vector multiplications which can be computed efficiently on memory arrays in an analog fashion. This approach requires highly resistive memory devices $(> mathrm{M}Omega)$ with low resistance variability to implement DNN weight memories. We propose an optimized Spin-Orbit Torque MRAM (SOT-MRAM) as weight memory in Analog in-Memory Computing (AiMC) systems for DNN inference. In SOT-MRAM the write and read path are decoupled. This allows changing the MTJ resistance to the high levels required for AiMC by tuning the tunnel barrier thickness without affecting the writing. The target resistance level and variation are derived from an algorithm driven design-technology-co-optimization (DTCO) study. Resistance levels are obtained from IR-drop simulations of a convolutional neural network (CNN). Variation limits are obtained by testing two noise-resilient CNNs with conductance variability. Finally, we demonstrate experimentally that the requirements for analog DNN inference are met by SOT-MRAM stack optimization.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"82 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80544071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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