S. Subramanian, M. Hosseini, T. Chiarella, S. Sarkar, P. Schuddinck, B. Chan, D. Radisic, G. Mannaert, A. Hikavyy, E. Rosseel, F. Sebaai, A. Peter, T. Hopf, P. Morin, S. Wang, K. Devriendt, D. Batuk, G. Martinez, A. Veloso, E. Litta, S. Baudot, Y. Siew, X. Zhou, B. Briggs, E. Capogreco, J. Hung, R. Koret, A. Spessot, J. Ryckaert, S. Demuynck, N. Horiguchi, J. Boemmels
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引用次数: 31
Abstract
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.
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