T. Ali, K. Seidel, K. Kühnel, M. Rudolph, M. Czernohorsky, K. Mertens, R. Hoffmann, K. Zimmermann, U. Mühle, Johannes Müller, J. van Houdt, L. Eng
{"title":"一种新的基于双铁电层的MFMFIS效应场效应管,具有最优堆栈调谐,可用于神经形态应用的低功耗和高速NVM","authors":"T. Ali, K. Seidel, K. Kühnel, M. Rudolph, M. Czernohorsky, K. Mertens, R. Hoffmann, K. Zimmermann, U. Mühle, Johannes Müller, J. van Houdt, L. Eng","doi":"10.1109/VLSITechnology18217.2020.9265111","DOIUrl":null,"url":null,"abstract":"A Novel MFMFIS FeFET based on dual MFM/MFIS integration in a single gate stack is reported. The external top and bottom contacts, dual ferroelectric (FE) layers, and tailored MFM/MFIS area ratio $(\\mathrm{A}_{\\mathrm{FI}})$ shows flexible stack tuning for improved FeFET performance. A tradeoff between maximized MFM voltage and weaker FET channel inversion is notable in the ID(sat) as AFI decreases. A dual FE layer enables maximized MW and fine control of its size when MFM/MFIS switching contribution is tuned through AFI change. The merits of $\\mathrm{A}_{\\mathrm{FI}}$ tuning extends to low voltage switching with maximized MW size and extremely linear current change over a wide dynamic range at high symmetry of synaptic potentiation/depression. Reliability in terms of variability, temperature effects, endurance, and retention is reported. The MFMFIS concept is thoroughly discussed with insight on optimal stack tuning for improved FeFET characteristics.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A Novel Dual Ferroelectric Layer Based MFMFIS FeFET with Optimal Stack Tuning Toward Low Power and High-Speed NVM for Neuromorphic Applications\",\"authors\":\"T. Ali, K. Seidel, K. Kühnel, M. Rudolph, M. Czernohorsky, K. Mertens, R. Hoffmann, K. Zimmermann, U. Mühle, Johannes Müller, J. van Houdt, L. Eng\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265111\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Novel MFMFIS FeFET based on dual MFM/MFIS integration in a single gate stack is reported. The external top and bottom contacts, dual ferroelectric (FE) layers, and tailored MFM/MFIS area ratio $(\\\\mathrm{A}_{\\\\mathrm{FI}})$ shows flexible stack tuning for improved FeFET performance. A tradeoff between maximized MFM voltage and weaker FET channel inversion is notable in the ID(sat) as AFI decreases. A dual FE layer enables maximized MW and fine control of its size when MFM/MFIS switching contribution is tuned through AFI change. The merits of $\\\\mathrm{A}_{\\\\mathrm{FI}}$ tuning extends to low voltage switching with maximized MW size and extremely linear current change over a wide dynamic range at high symmetry of synaptic potentiation/depression. Reliability in terms of variability, temperature effects, endurance, and retention is reported. The MFMFIS concept is thoroughly discussed with insight on optimal stack tuning for improved FeFET characteristics.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"13 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265111\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Dual Ferroelectric Layer Based MFMFIS FeFET with Optimal Stack Tuning Toward Low Power and High-Speed NVM for Neuromorphic Applications
A Novel MFMFIS FeFET based on dual MFM/MFIS integration in a single gate stack is reported. The external top and bottom contacts, dual ferroelectric (FE) layers, and tailored MFM/MFIS area ratio $(\mathrm{A}_{\mathrm{FI}})$ shows flexible stack tuning for improved FeFET performance. A tradeoff between maximized MFM voltage and weaker FET channel inversion is notable in the ID(sat) as AFI decreases. A dual FE layer enables maximized MW and fine control of its size when MFM/MFIS switching contribution is tuned through AFI change. The merits of $\mathrm{A}_{\mathrm{FI}}$ tuning extends to low voltage switching with maximized MW size and extremely linear current change over a wide dynamic range at high symmetry of synaptic potentiation/depression. Reliability in terms of variability, temperature effects, endurance, and retention is reported. The MFMFIS concept is thoroughly discussed with insight on optimal stack tuning for improved FeFET characteristics.