Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs

Abstract

In this work, we demonstrate FDSOI ferroelectric FETs (FeFETs) incorporating 4.5 nm hafnium zirconium oxide, which show a ~0.5V memory window at +/-3.3V and a program/erase speed of 1 $\mu \mathrm{s}$. In typical FeFETs where $\geq 9$ nm thick ferroelectric (FE) gate oxides have been used, bulk charge trapping has been identified as the main mechanism for endurance degradation and shrinkage of the memory window (MW). By contrast, we find that the role of bulk trapping in our devices with a much thinner FE layer is minimal. Through a combination of cryogenic temperature-dependent electrical measurements and simulations using the Ginestra ™ modeling platform, we identify and prove that hot electron-induced hole damage during the application of negative gate biases is the primary source of endurance degradation and MW closure in FeFETs with scaled oxide layers.