Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM with 10 ns Low Power Write Operation, 10 years Retention and Endurance $> 10^{11}$

Abstract

We have firstly fabricated quad-interface perpendicular MTJ (Quad-MTJ) down to 33 nm with our developed PVD, RIE and damage control integration process technologies under 300 mm process. Secondly, we demonstrated scalability merit as well as high speed writing of Quad-MTJ compared with double-interface p-MTJ (Double-MTJ) as follows; (a) two times larger thermal stability factor $\Delta(1\mathrm{X}$ nm Quad- MTJ is extrapolated to achieve 10 years retention.), (b) lower write voltage at short write pulse regions at less than 30 ns, (c) in scaled MTJ, effective suppression of write current increase for higher write speed, (d) more than 2 times higher write efficiency at 10ns write operation down to 33 nm MTJ. Finally, we revealed that our developed 33 nm Quad-MTJ achieve excellent endurance of more 1011 thanks to higher write efficiency and low damage integration process technology. These results show that the Quad-MTJ technology is one of promising way for low power, high speed and enough reliable STT -MRAM with excellent scalability down to 1X nm node.