B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen, R. Maurand, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard
{"title":"28nm FD-SOI技术在低至100mK低温下的量子计算变异性评估","authors":"B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen, R. Maurand, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard","doi":"10.1109/VLSITechnology18217.2020.9265034","DOIUrl":null,"url":null,"abstract":"Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $\\mathrm{I}_{\\mathrm{ON}} > 1\\mathrm{mA}\\mu \\mathrm{m}$ and $\\mathrm{I}_{\\mathrm{OFF}}$ below the equipment accuracy <1 fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (R T) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage $(\\mathrm{V}_{\\mathrm{TH}})$ and current gain factor $(\\beta)$ variabilities. Besides that, we demonstrated that the increase of $\\mathrm{V}_{\\mathrm{TH}}$ and $\\beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.","PeriodicalId":6850,"journal":{"name":"2020 IEEE Symposium on VLSI Technology","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing\",\"authors\":\"B. C. Paz, L. L. Guevel, M. Cassé, G. Billiot, G. Pillonnet, A. Jansen, R. Maurand, S. Haendler, A. Juge, E. Vincent, P. Galy, G. Ghibaudo, M. Vinet, S. de Franceschi, T. Meunier, F. Gaillard\",\"doi\":\"10.1109/VLSITechnology18217.2020.9265034\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $\\\\mathrm{I}_{\\\\mathrm{ON}} > 1\\\\mathrm{mA}\\\\mu \\\\mathrm{m}$ and $\\\\mathrm{I}_{\\\\mathrm{OFF}}$ below the equipment accuracy <1 fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (R T) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage $(\\\\mathrm{V}_{\\\\mathrm{TH}})$ and current gain factor $(\\\\beta)$ variabilities. Besides that, we demonstrated that the increase of $\\\\mathrm{V}_{\\\\mathrm{TH}}$ and $\\\\beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.\",\"PeriodicalId\":6850,\"journal\":{\"name\":\"2020 IEEE Symposium on VLSI Technology\",\"volume\":\"40 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSITechnology18217.2020.9265034\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSITechnology18217.2020.9265034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $\mathrm{I}_{\mathrm{ON}} > 1\mathrm{mA}\mu \mathrm{m}$ and $\mathrm{I}_{\mathrm{OFF}}$ below the equipment accuracy <1 fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (R T) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage $(\mathrm{V}_{\mathrm{TH}})$ and current gain factor $(\beta)$ variabilities. Besides that, we demonstrated that the increase of $\mathrm{V}_{\mathrm{TH}}$ and $\beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.