Immersion in Memory Compute (ImMC) Technology

Abstract

Immersion in Memory Compute (ImMC) technology with multiple chips and functions in multi-layer stacking integrated using System on Integrated Chips (SoIC™) technology is presented. The technology provides multiple compute and memory chips to interconnect each other to gain computing power and memory bandwidth. The interconnect parasitics, bandwidth density and power efficiency are analyzed using N7 light IO transceiver. The ImMC compared with 3DIC with bridge and with shared die, respectively, using $\mu \mathrm{bump}$ and TSV, is studied. The ImMC is 16x, 14x, and 224x better than the 3DIC with bridge in bump density, data rate, and bandwidth density. The transceiver power and size for the ImMC is only 1 % of those for the 3DIC.