All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors

We evidence a unique feature of junctionless Fully-Depleted Silicon-On-Insulator (JL FDSOI) transistors: the presence of both bulk and accumulation conduction renders standard VT-variability studies incomplete. For JL transistors, we rather propose an original analysis of the (local and global) variability in all-operation-regimes, from subthreshold to accumulation. We evidence that the current variability around VT is highly sensitive to back-bias VB and film thickness $(\mathrm{t}_{\mathrm{si}})$ uniformity. We demonstrate experimentally for the first time up to 70% lower drain current (ID) local variability for Junctionless Accumulation Mode (JAM) vs. inversion mode (IM) at 1V gate voltage (V G), $\mathrm{L}=18$ nm gate length and $\mathrm{W}=20\mathrm{nm}$ width. This is attributed to the impurity screening, lowering the impact of Random Dopant Fluctuations variability.