Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry

Abstract

An interpretable neural network (NN) is used to model the self-heating (SH) in complex FinFET circuits. The NN training/testing datasets from 3 -stage to 37 -stage chain circuits in folded layout composed of inverter (INV)/NAND/NOR are simulated by our distributed $\mathrm{R}_{\mathrm{th}}-\mathrm{C}_{\mathrm{th}}$ SPICE model [1], [2]. The interfacial thermal resistance [3], boundary scattering [4], alloy scattering [5], and layout dependence are considered. The NN interpretation by feature importance analysis is consistent with the thermal physics. Stage# is the most important feature of the NN prediction. Both via2 bundle positions and via2 numbers (via2#) are effective to reduce SH. As compared to SPICE, NN prediction in 37 -stage INV chain computes $3\mathrm{x}10^{6}\mathrm{X}$ faster with accuracy loss $< 1^{\circ}\mathrm{C}$. The high computation efficiency and high precision make NN feasible to predict chain circuits up to 40 stages, which cannot be simulated by SPICE due to long computation time.