Integration-The Vlsi Journal最新文献_第4页

Analysis and implementation of a novel parametrically controllable spherical multi-scroll memristive conservative hyperchaotic system 一种新型参数可控球形多涡旋记忆保守超混沌系统的分析与实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-15 DOI: 10.1016/j.vlsi.2025.102409

Yizhe Li, Mu Li

引用次数: 0

A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters 应用一种新的本征参数相关增强技术精确提取GaN HEMT小信号模型参数

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-15 DOI: 10.1016/j.vlsi.2025.102411

Jincan Zhang, Haiyi Cai, Shaowei Wang, Min Liu

{"title":"A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters","authors":"Jincan Zhang, Haiyi Cai, Shaowei Wang, Min Liu","doi":"10.1016/j.vlsi.2025.102411","DOIUrl":"10.1016/j.vlsi.2025.102411","url":null,"abstract":"<div><div>In this paper, a novel intrinsic-parameters-correlation-enhancement method combining Principal Component Analysis (PCA) algorithm and Particle Swarm Optimization (PSO) algorithm for extracting intrinsic parameters of GaN High Electron Mobility Transistors (HEMT) is proposed. The traditional intrinsic parameter extraction methods are time-consuming and have low accuracy for modeling <em>S</em>-parameter. In order to improve the model accuracy, the PSO algorithm can be used to optimize the intrinsic parameters. However, the PSO algorithm does not consider the correlation of the intrinsic parameters, which leads to a limited improvement in model accuracy. To further improve the model accuracy, in this paper, the PCA algorithm is used to process the real and imaginary parts of the intrinsic model <em>Y</em>-parameters, which can enhance the correlation between intrinsic parameters. Then, the new intrinsic model <em>Y</em>-parameters and the PSO algorithm are used to extract the intrinsic parameters. To validate the effective of the proposed technology, it is applied to extract GaN HEMT small-signal model parameters in the frequency range of 0.5–20.5 GHz, and the experimental results show that the <em>S</em>-parameter modeling accuracy is effectively improved.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102411"},"PeriodicalIF":2.2,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach 使用体积记忆网络的纸质数字生物芯片流体控制协同设计：一种预测建模方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-14 DOI: 10.1016/j.vlsi.2025.102408

G. Brindha , Preeti Narooka , M.K. Prathiba , Suhasini S. Goilkar

{"title":"Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach","authors":"G. Brindha , Preeti Narooka , M.K. Prathiba , Suhasini S. Goilkar","doi":"10.1016/j.vlsi.2025.102408","DOIUrl":"10.1016/j.vlsi.2025.102408","url":null,"abstract":"<div><div>The growing popularity of paper-based digital microfluidic biochips (P-DMFBs) is attributed to their low cost and ease of fabricating electrodes and control circuits on a sheet of paper using inkjet printer and conductive ink. The complex design guidelines are employed for complete design viability, such as preventing induced control interference, reducing control line spacing, and guaranteeing congestion-free wiring in single layer. It takes careful consideration of cost-raising aspects, like wire length, schedule length, control pin count to achieve an effective fluid-control codesign. Therefore, Fluid-Control Codesign for Paper-dependent Digital Biochips using Volumetric Memory Networks: A Predictive Modelling Approach (FCC-DB-VMN) is proposed in this paper. This work offers a technique for pin-constrained P-DMFBs based on Volumetric Memory Networks that predict errors in control design and guides FCC to solve issues that drive costs while achieving congestion with conflict-free wiring. A low-cost platform is produced by this Volumetric Memory Networks (VMN) by eliminating design cycles. The proposed technique is evaluated using a balanced dataset. The proposed FCC-DB-VMN attains 20.67 %, 32.30 % and 18.52 % higher coefficient of accuracy, 15.03 %, 25.12 % and 25.64 % lower RMSE when compared with existing models: Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-dependent Digital Microfluidic Biochips (RL-DDQN-DMB), An integrated co-design of flow-dependent biochips considering flow-control design issues and objectives (ICD-FB-FCD), and Physical design for microfluidic biochips considering actual volume management along channel storage (PD-MFD-VMCS) respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102408"},"PeriodicalIF":2.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143679062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS 基于微调时基自适应采样技术的低功耗SAR ADC在180nm CMOS上的心电监测应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-14 DOI: 10.1016/j.vlsi.2025.102407

Naveen Kandpal, Anil Singh, Alpana Agarwal

{"title":"A low power SAR ADC with fine–tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS","authors":"Naveen Kandpal, Anil Singh, Alpana Agarwal","doi":"10.1016/j.vlsi.2025.102407","DOIUrl":"10.1016/j.vlsi.2025.102407","url":null,"abstract":"<div><div>This work proposes an adaptive sampling SAR Analog-to-Digital converter (ADC) with a novel fine-tuned time-based sampling technique to dynamically adjust the sample rate for normal and abnormal ECG signals based on the characteristics of the incoming ECG signal. By integrating machine learning, the ADC adapts to varying signal conditions, ensuring accurate capture of essential data while maintaining energy efficiency, thereby enhancing the effectiveness of portable and wearable health monitoring devices. Unlike conventional methods, the Analog front end uses a time-based technique that effectively identifies and digitizes all critical information present in ECG signals. Additionally, the ADC incorporates a variable resolution scheme, enhancing power efficiency and reducing data bandwidth. The ADC adaptively allocates more bits to the most significant portions of the ECG waveform while reducing the resolution for less critical segments by employing a time-based approach. This enables efficient data representation and reduces overall data transfer requirements, making this architecture more power-efficient. Implemented in 180 nm CMOS technology, the proposed ADC consumes only 498.6 μW with a 1.8 V supply and achieves ENOB of 5.21 bits, SNDR of 31.76 dB, and SFDR of 44.31 dB. The sampling frequency of the proposed architecture changes from 64 Hz to 512 Hz, which is suitable for portable ECG monitoring applications. The FoM of the proposed work ranges from 100 to 262 fj/conversion-step for 64–512 Hz sampling rate, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102407"},"PeriodicalIF":2.2,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143636643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Network traffic inspection to enhance anomaly detection in the Internet of Things using attention-driven Deep Learning 利用注意力驱动深度学习增强物联网异常检测的网络流量检测

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-13 DOI: 10.1016/j.vlsi.2025.102398

Mireya Lucia Hernandez-Jaimes , Alfonso Martinez-Cruz , Kelsey Alejandra Ramírez-Gutiérrez , Alicia Morales-Reyes

{"title":"Network traffic inspection to enhance anomaly detection in the Internet of Things using attention-driven Deep Learning","authors":"Mireya Lucia Hernandez-Jaimes , Alfonso Martinez-Cruz , Kelsey Alejandra Ramírez-Gutiérrez , Alicia Morales-Reyes","doi":"10.1016/j.vlsi.2025.102398","DOIUrl":"10.1016/j.vlsi.2025.102398","url":null,"abstract":"<div><div>Anomaly detection methods are being developed to enhance the security of the Internet of Things (IoT) in the healthcare sector, particularly against cyberattacks targeting network vulnerabilities. On the other hand, supervised Machine learning (ML) algorithms have been leveraged because of their potential to handle large amounts of data and identify patterns. However, their effectiveness in identifying unknown attacks is uncertain, and the limited labeled data in the Internet of Medical Things (IoMT) environments challenges the adoption of these methods. In response, unsupervised ML-based anomaly detection methods have been proposed. Unfortunately, their performance remains suboptimal compared to supervised ML and unsupervised Deep Learning (DL) models due to the challenges posed by the heterogeneous nature of IoT data, which complicates the extraction and selection of relevant network traffic features—critical processes to ensure the effectiveness of these methods. To address these challenges, this study proposes a novel attention-driven deep neural network algorithm for network traffic representation, resulting in an improved unsupervised anomaly detection performance of the One-Class Support Vector Machine and performance comparable to current unsupervised DL-based methods. This novel network traffic characterization method relies on just nine generic features and the knowledge of which communication protocols are present or absent by applying principles from two natural language processing techniques. On the CICIoMT2024 dataset, our proposal achieves a precision of 84.43%, a recall of 98.73%, and an F1-score of 91.02%. On the MQTT-IoT-IDS2020 dataset, we achieve 92.14%, 99.17%, and 95.53% of precision, recall, and F1-score, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102398"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143678932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems 基于人工神经网络和混沌系统的新型加密安全伪随机数生成器的设计与FPGA实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-08 DOI: 10.1016/j.vlsi.2025.102388

Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi

{"title":"Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems","authors":"Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi","doi":"10.1016/j.vlsi.2025.102388","DOIUrl":"10.1016/j.vlsi.2025.102388","url":null,"abstract":"<div><div>A secure random number generator (RNG) is crucial for cryptography and data protection applications. Many existing approaches employ classical chaotic systems, which have been demonstrated as vulnerable to some attacks. Therefore, this research proposes the design on FPGA of a new pseudo-RNG based on an artificial neural network (ANN) and chaotic systems. Initially, a multi-layer perceptron (MLP) with a hardware friendly activation function (AF) is trained to mimic the behavior of the unified chaotic system (UCS). To mitigate chaos degradation and the difference between the training and the inference, the scheduled sampling technique is adapted and applied to the MLP network. Once the model is well-tuned, its chaotic nature is validated by calculating the Lyapunov exponents and determining the fractal dimension. The pre-trained model based on which an MLP-based Chaotic Pseudo-RNG (MLP-CPRNG) is then implemented on FPGA using VHDL language and Xilinx Vivado design suite. To improve the generator’s output capabilities, a technique named the <span><math><mi>d</mi></math></span>-lagged differencing (<span><math><mi>d</mi></math></span>-LD) is implemented as a part of the MLP-CPRNG. The implemented MLP-CPRNG outperforms the existing works in terms of resource utilization, which makes it suitable for resource-constrained environment. It also offers extended key space and has successfully passed performance tests such as NIST statistical tests, entropy measurement, and correlation analysis. These results highlight the robustness of MLP-CPRNG against brute-force, algebraic and statistical attacks, thus its suitability for embedded cryptographic applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102388"},"PeriodicalIF":2.2,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard CCSDS近地标准的资源高效和超高吞吐量LDPC解码器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-07 DOI: 10.1016/j.vlsi.2025.102390

Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li

{"title":"Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard","authors":"Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li","doi":"10.1016/j.vlsi.2025.102390","DOIUrl":"10.1016/j.vlsi.2025.102390","url":null,"abstract":"<div><div>This paper presents a resource-efficient, ultra-high throughput low density parity check (LDPC) decoder that is suitable for tens of gigabit bits per second satellite communications. To address routing congestion and critical path delay, which are typically caused by the high degree of parallelism in high throughput decoder designs, this work introduces an efficient computation circuit for identifying the two minimum values in the check node update process. Furthermore, a non-uniform quantization method based on mutual information maximization is proposed for log-likelihood ratio (LLR) representation, enabling a more favorable trade-off between decoding performance and implementation complexity. Additionally, the decoder utilizes a pipelined multi-frame parallel scheduling scheme, which significantly boosts throughput with only a slight increase in storage requirements. Finally, the proposed design is implemented and tested on a Xilinx UltraScale+ XCVU13P FPGA. The results show that the decoder achieves a throughput of 76.5Gbps at 8 iterations and 200MHz. This implementation outperforms existing designs, highlighting the innovative and superior nature of our approach.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102390"},"PeriodicalIF":2.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant 基于apsamry常数的新型超混沌系统发生器的设计与实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102399

Omer Kocak , Uğur Erkan , Ismail Babaoglu

{"title":"Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant","authors":"Omer Kocak , Uğur Erkan , Ismail Babaoglu","doi":"10.1016/j.vlsi.2025.102399","DOIUrl":"10.1016/j.vlsi.2025.102399","url":null,"abstract":"<div><div>Modern chaotic systems necessitate high levels of randomness and complexity, which can be achieved through adaptable seed functions. This paper proposes a new 2D Apéry chaotic system generator (2D-ACG) based on Apéry numbers to fulfill this need. The 2D-ACG generates various chaotic systems using classical seed functions. The effectiveness and the capabilities of 2D-ACG are demonstrated on three well-known example chaotic maps using pairs of seed functions such as Cos-Cos, Sin-Sin and Cos-Sin. The reliability of chaos metrics, such as the Lyapunov exponent (LE), sample entropy (SE), correlation dimension (CD), Kolmogorov entropy (KE), C0 test, and sensitivity, confirms the chaotic performance of these maps. This is further supported by a comparison with reported 2D chaotic systems. Furthermore, one of the maps derived from 2D-ACG has been implemented into an image encryption algorithm and has successfully passed the cryptanalysis tests. Additionally, the hardware implementation of 2D-ACG has been tested on a field programmable gate array (FPGA), thereby confirming its efficacy. The superior results obtained indicate that the proposed 2D-ACG, with its enhanced diversity and complex structure derived from the Apéry's constant, exhibits higher-performance chaotic characteristics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102399"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143609484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application 一种用于ZigBee应用的低功耗、低pdp双模CML分频器的设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102400

Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab

{"title":"Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application","authors":"Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab","doi":"10.1016/j.vlsi.2025.102400","DOIUrl":"10.1016/j.vlsi.2025.102400","url":null,"abstract":"<div><div>This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g<sub>m</sub> over I<sub>d</sub> (g<sub>m</sub>/I<sub>d</sub>) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102400"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143579833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains 丰富的动态和模拟实现的Hopfield神经网络在整数和分数阶域

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102389

Diego S. de la Vega , Jesus M. Munoz-Pacheco , Olga G. Félix-Beltrán , Christos Volos

引用次数: 0