Integration-The Vlsi Journal最新文献_第4页

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ √(H z) noise and 190.47 nW micro-power for ECG applications 用于心电图应用的新型可调电容表列仪表放大器，噪声为 14.4 nV/√（H z），微功率为 190.47 nW

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-30 DOI: 10.1016/j.vlsi.2024.102268

{"title":"A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ √(H z) noise and 190.47 nW micro-power for ECG applications","authors":"","doi":"10.1016/j.vlsi.2024.102268","DOIUrl":"10.1016/j.vlsi.2024.102268","url":null,"abstract":"<div><p>This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) g<sub>m</sub> enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm<sup>2</sup> of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142128398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications 用于提高毫米波应用 CMOS 射频集成电路面积效率的不规则八边形片上电感器实验分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-24 DOI: 10.1016/j.vlsi.2024.102259

{"title":"Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications","authors":"","doi":"10.1016/j.vlsi.2024.102259","DOIUrl":"10.1016/j.vlsi.2024.102259","url":null,"abstract":"<div><p>This article deals with the analysis of irregularly shaped single turn octagonal spiral inductors for millimeter-wave and sub-THz CMOS IC designs. Simulations and experimental results, along with theoretical formulations, are used to characterize these irregular structures. This article proposes a novel approach for efficient use of silicon chip area by reshaping the on-chip inductors used in millimeter wave (mm-wave) applications without compromising the performance of the inductors. Especially in CMOS RFICs when a space constraint exists in either <span><math><mi>X</mi></math></span>- or <span><math><mi>Y</mi></math></span>-direction in their layout, such reshaping can be attempted. Moreover, two novel methods of reshaping the inductors are proposed and studied thoroughly. The study of these irregular shapes has interesting conclusions, which are validated through on-wafer measurements. Certain methods of reshaping result in inductors which do not have degradation in their quality factors (<span><math><mi>Q</mi></math></span>), while other approaches degrade the <span><math><mi>Q</mi></math></span>. Based on these insights, a design methodology is proposed for designers who need to reshape their inductors to irregular structures while not compromising on the quality factor. The measurement results agree with the simulations and prove that the proposed reshaping is practically possible.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow 使用嵌入 DFT 流程的专用 Pure MaxSAT 求解器的快速测试压实方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-22 DOI: 10.1016/j.vlsi.2024.102265

{"title":"A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow","authors":"","doi":"10.1016/j.vlsi.2024.102265","DOIUrl":"10.1016/j.vlsi.2024.102265","url":null,"abstract":"<div><p>Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Clock mesh synthesis through dynamic programming with physical parameters consideration 通过考虑物理参数的动态编程合成时钟网格

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-19 DOI: 10.1016/j.vlsi.2024.102261

引用次数: 0

Pre-route timing prediction and optimization with graph neural network models 利用图神经网络模型进行预路由时序预测和优化

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-19 DOI: 10.1016/j.vlsi.2024.102262

{"title":"Pre-route timing prediction and optimization with graph neural network models","authors":"","doi":"10.1016/j.vlsi.2024.102262","DOIUrl":"10.1016/j.vlsi.2024.102262","url":null,"abstract":"<div><p>In recent years, the application of deep learning (DL) models has sparked considerable interest in timing prediction within the place-and-route (P&R) flow of IC chip design. Specifically, at the pre-route stage, an accurate prediction of post-route timing is challenging due to the lack of sufficient physical information. However, achieving precise timing prediction significantly accelerates the design closure process, saving considerable time and effort. In this work, we propose pre-route timing prediction and optimization framework with graph neural network (GNN) models combined with convolution neural network (CNN). Our framework is divided into two main stages, each of which is further subdivided into smaller steps. Precisely, our GNN-driven arc delay/slew prediction model is divided into two levels: in level-1, it predicts net resistance (net R) and net capacitance (net C) using GNN while the arc length is predicted using CNN. These predictions are hierarchically passed on to level-2 where delay/slew is estimated with our GNN based prediction model. The timing optimization model utilizes the precise delay/slew predictions obtained from the GNN-driven prediction model to accurately set the path margin during the timing optimization stage. This approach effectively reduces unnecessary turn-around iterations in the commercial EDA tools. Experimental results show that by using our proposed framework in P&R, we are able to improve the pre-route prediction accuracy by 42%/36% on average on arc delay/slew, and improve timing metrics in terms of WNS, TNS, and the number of timing violation paths by 77%, 77%, and 64%, which are an increase of 32%/35% on arc delay/slew and 30%, 20% and 31% on timing optimization compared with the existing DL prediction model.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142044946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A fast and high-performance global router with enhanced congestion control 快速、高性能的全局路由器，具有增强的拥塞控制功能

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-17 DOI: 10.1016/j.vlsi.2024.102263

{"title":"A fast and high-performance global router with enhanced congestion control","authors":"","doi":"10.1016/j.vlsi.2024.102263","DOIUrl":"10.1016/j.vlsi.2024.102263","url":null,"abstract":"<div><p>In global routing, congestion and running time are the key factors that affect the quality of the solution. With the rapid growth of integrated chip scale, striking a balance between running time and congestion has become a bottleneck in improving design quality. In this paper, we propose a highly efficient and effective global router to address this challenge. We first propose an efficient R-tree-based compatible routing region partitioning algorithm for collecting routable regions, which offers robust support for ideal parallel routing scheduling. Then, taking into account the effect of the barrel effect on congestion evaluation and the detrimental impact of loops, a congestion-driven initial parallel routing scheme is proposed to enhance routability in the triaxial pattern routing structure. After that, we develop an accurate congestion estimation model and an optimized path-searching scheme, which are instrumental in effectively managing smaller congestion gradient variations and guiding efficient congestion reduction. We evaluate the performance of our algorithm on the ISPD 2018 and ISPD 2019 contest benchmark suites and compare it with the state-of-the-art work. Experimental results show that our proposed algorithm significantly reduces 71% overflows, improving 65% running time, and the total wirelength is even smaller.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142050087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application 用于超低功耗应用的栅极周围碳纳米管场效应晶体管支持差异级联通过晶体管绝热逻辑

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-14 DOI: 10.1016/j.vlsi.2024.102260

{"title":"Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application","authors":"","doi":"10.1016/j.vlsi.2024.102260","DOIUrl":"10.1016/j.vlsi.2024.102260","url":null,"abstract":"<div><p>Advances in wearable technology, IoT, and mobile applications have increased the demand for ultra-low-power electronic devices. Adiabatic Logic Circuit (ALC) is a design technique utilized in digital circuits to decrease the power consumption by decreasing the dynamic power dissipation. Current technologies face challenges in achieving both high performance and ultra-low power consumption. This research work introduces a novel approach in digital circuit design, specifically the Gate All-around Carbon Nanotube Field Effect Transistor with Discrepancy Cascode Pass Transistor Adiabatic Logic (GAA-CNTFET-DCPTAL), tailored for ultra-low power applications. This design operates efficiently with a four-phase Power Clock (PC) and demonstrates remarkable performance by achieving operation frequencies of up to 1 GHz while minimizing energy dissipation. GAA-CNTFET provides superior electrostatic control and high carrier mobility, reducing leakage currents and enhancing switching speeds. Simultaneously, Discrepancy Cascode Pass Transistor Adiabatic Logic (DCPTAL) uses adiabatic logic principles and a cascode structure to minimize energy dissipation during switching events. The technology node of proposed model is 10 nm. The software used for assessment is HSPICE is used for the simulation and validation of the proposed design. The proposed GAA-design attains 25.36 %, 14.28 %, and 16.06 % lower average power analyzed with existing techniques, such as Design with Evaluation of Clocked Differential Adiabatic Logic Families for the applications of low Power (DE-CDAL-LPA), Adiabatic logic-base strong ARM comparator for ultra-low power applications (AL-SARM-ULPA) and Analysis of 2PADCL Energy Recovery Logic for Ultra Low Power VLSI Design for SOC with Embedded Applications (2PADCL-ULP-VLSI) respectively.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator 利用压控振荡器实现全集成的蔡氏混沌记忆电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-12 DOI: 10.1016/j.vlsi.2024.102258

引用次数: 0

A fast hardware accelerator for nighttime fog removal based on image fusion 基于图像融合的夜间除雾快速硬件加速器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-08 DOI: 10.1016/j.vlsi.2024.102256

引用次数: 0

Efficient deployment of Single Shot Multibox Detector network on FPGAs 在 FPGA 上高效部署单发多箱探测器网络

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-08 DOI: 10.1016/j.vlsi.2024.102255

{"title":"Efficient deployment of Single Shot Multibox Detector network on FPGAs","authors":"","doi":"10.1016/j.vlsi.2024.102255","DOIUrl":"10.1016/j.vlsi.2024.102255","url":null,"abstract":"<div><p>FPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. However, contemporary FPGA designs often come with high costs and resource demands, which limit their adoption in resource-constrained embedded and edge devices. This study presents a novel design that addresses these limitations by emphasizing cost-effectiveness, energy efficiency, and rapid performance, particularly for single-shot multi-box detectors. The design employs an Xilinx ZYNQ7020-based main control chip and leverages parallel computing models for convolution layers and feature extraction. It enhances efficiency by proposing parallel feature extraction at the network architecture level and integrates convolution activation and pooling in a single, hardware-optimized operation for convolution kernel computations. The design employs alternating memory reuse for feature layer inputs and outputs to optimize memory management, thereby reducing read/write delays and transmission times. Implemented on a PYNQ-Z2 development board and tested using Jupyter Notebook, the SSD algorithm demonstrates a 789.4 GOPS inference performance with 16-bit fixed-point quantization at a 200MHz clock frequency, achieving an average accuracy of 77.84% and an inference time of 81.4621 ms, while consuming 1.595 watts of power. This innovative design significantly boosts energy efficiency by up to 2590%, outperforming contemporary methods.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141979893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0