Integration-The Vlsi Journal最新文献_第4页

An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology 基于0.18 μm CMOS技术的S到Ku波段宽带低压低功耗上转换混频器

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-07 DOI: 10.1016/j.vlsi.2025.102536

Jun-Da Chen, Liang-Chung Shen

引用次数: 0

RapidPnR: Accelerating the physical design for FPGAs via design-level parallelism RapidPnR：通过设计级并行加速fpga的物理设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-04 DOI: 10.1016/j.vlsi.2025.102532

Wanzheng Weng, Pingqiang Zhou

引用次数: 0

FPGA routing congestion prediction combining DAGNN and GCN 结合DAGNN和GCN的FPGA路由拥塞预测

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-03 DOI: 10.1016/j.vlsi.2025.102530

Tingyuan Nie, Yang Du, Da Guo, Kun Zhao

{"title":"FPGA routing congestion prediction combining DAGNN and GCN","authors":"Tingyuan Nie, Yang Du, Da Guo, Kun Zhao","doi":"10.1016/j.vlsi.2025.102530","DOIUrl":"10.1016/j.vlsi.2025.102530","url":null,"abstract":"<div><div>The issue of routing congestion is intractable due to the high complexity of FPGA (Field-Programmable Gate Array) design. Accurately predicting routing congestion in the early stages of the design process can shorten the overall design cycle. In the placement stage, this paper proposes an FPGA routing congestion prediction framework combining a deep adaptive graph neural network (DAGNN) and a graph convolutional network (GCN), the so-called DAGNN-GCN. DAGNN captures deep neighborhood topological information, focusing primarily on complex network features. Based on the hierarchical inclusion relationship between G-cells and cells, the extracted topological information is mapped geometrically onto the original geometric features and inflated to generate input feature vectors. These vectors are then fed into the GCN to train the routing congestion prediction of the model. Experimental results on the ISPD 2016 dataset demonstrate that the proposed method achieves Kendall, Spearman, and Pearson correlation coefficients of 0.57, 0.72, and 0.76, respectively, representing improvements of 16.33%, 5.88%, and 13.43% over the state-of-the-art LHNN method. Ablation studies further validate the efficiency of the proposed features in routing congestion prediction.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102530"},"PeriodicalIF":2.5,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145003689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of dynamic prairie dog optimization based variable length conditional counter enabled multiplier with improved slack time and power 基于动态草原土拨鼠优化的变长条件计数乘法器的设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-03 DOI: 10.1016/j.vlsi.2025.102535

K. Yogeshwaran , S. Suresh

{"title":"Design of dynamic prairie dog optimization based variable length conditional counter enabled multiplier with improved slack time and power","authors":"K. Yogeshwaran , S. Suresh","doi":"10.1016/j.vlsi.2025.102535","DOIUrl":"10.1016/j.vlsi.2025.102535","url":null,"abstract":"<div><div>Multipliers are major components in any data rendering, logical computations and the unit of Digital Signal Processing (DSP). The particular events counting carried out by using the electronic devices called Binary Counters (BC) that displays as well as stores the count numbers. While providing an effective counting operation, the Binary Counter (BC) incorporates a sequential logic circuit with a clock signal. This work presented a novel Variable Length Conditional Counter (VLCC) design using the Dynamic Prairie Dog Optimization (DPDO) algorithm for delay mitigation. Using the proposed DPDO algorithm, this study performs path delay reduction, enhances the slack interval, and designs the multiplier at various frequencies. The circuit based slack interval evaluates the frequency operation maximization. To compare state-of-the-art works, the slack time performance analyzed and implementation handles based on Mentor Graphics EDA simulator. CMOS technology effectuates 8-bit binary multiplier implementation. The slack time enhancement as well as computational delay mitigation performances of proposed DPDO algorithm performance surpassed other state-of-the-art works.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102535"},"PeriodicalIF":2.5,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ATSS-PUF with hardware sharing for secure in-situ memory circuit 具有硬件共享的ATSS-PUF，用于安全的原位存储电路

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-03 DOI: 10.1016/j.vlsi.2025.102524

Shutong Zhang , Pengjun Wang , Mengfan Xv , Bo Chen , Yuejun Zhang

{"title":"ATSS-PUF with hardware sharing for secure in-situ memory circuit","authors":"Shutong Zhang , Pengjun Wang , Mengfan Xv , Bo Chen , Yuejun Zhang","doi":"10.1016/j.vlsi.2025.102524","DOIUrl":"10.1016/j.vlsi.2025.102524","url":null,"abstract":"<div><div>Industrial Internet of Things (IoT) edge nodes urgently need encryption schemes that take into account key stability and hardware efficiency under low-power consumption and harsh working conditions, but existing technologies are limited by defects such as high key BER, high hardware resource overhead, and insufficient data security. To solve these problems, this paper proposes a four-mode reconfigurable in-situ memory unit, which accomplishes the hardware multiplexing of key generation, dynamic screening, heterodyne encryption and dense state storage functions, and combines the active time-tilted screening mechanism with the injection of controlled delayed perturbations into the symmetric path to screen the unstable key bits. The measured results demonstrate that the circuit PUF response drops to 1.9 % and 2.9 % BER under temperature fluctuation of −20 °C–80 °C and voltage perturbation of 0.7–1.2V, respectively, and the randomness of the PUF response reaches 99.8 %, the inter-slice Hamming distance reaches 49.57 %, the autocorrelation is only 0.0224, which passes the randomness test of NIST, and the capability of anti-side-channel attack and anti-brutal attack is provided.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102524"},"PeriodicalIF":2.5,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a SRAM memory cell with enhanced stability and variability for embedded biomedical applications 嵌入式生物医学应用中具有增强稳定性和可变性的SRAM存储单元的设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-03 DOI: 10.1016/j.vlsi.2025.102537

Aditya Soni , Sagar Juneja , M. Elangovan , Kulbhushan Sharma

{"title":"Design of a SRAM memory cell with enhanced stability and variability for embedded biomedical applications","authors":"Aditya Soni , Sagar Juneja , M. Elangovan , Kulbhushan Sharma","doi":"10.1016/j.vlsi.2025.102537","DOIUrl":"10.1016/j.vlsi.2025.102537","url":null,"abstract":"<div><div>Embedded biomedical applications need low-power of operation and high-speed to meet the requirements of portability and fast response time. This can be achieved by improving the design of embedded memories. An SRAM cell has been reported in this work with eleven 18 nm FinFET devices. To minimize the write delay, transmission gate approach is used, which also improves the variability performance as analyzed through Monte Carlo simulations. Leakage control transistors and pmos-pmos-nmos (PPN) based inverters have been incorporated to reduce power and improve pull-up strength, respectively. Read decoupling technique has been used to separate the read-write operations. Titled as 11TLCTG SRAM cell, the design is analyzed using Cadence Virtuoso tool and the effects of process corners-voltage-temperature (PVT) variations are studied as well. It has a power consumption of 18.01 nW, 20.91 nW, and 3.58 μW during write, hold and read operations, respectively, and has excellent stability parameter values. Its write stability is 1.36x, 1.47x, 1.23x, 5.54x and 1.09x better and read stability is 2x, 1.04x, 1.04x, 1.23x, and 2.09x better than that of the contemporary designs considered for comparison purposes. The proposed design occupies the area of 4.7 μm<sup>2</sup> and mitigates half select issues, which makes it ideal for building large memory arrays.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102537"},"PeriodicalIF":2.5,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145003688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs 3D noc中热与拥塞感知无死锁应用的新型停止路由策略

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-02 DOI: 10.1016/j.vlsi.2025.102534

Priyajit Mukherjee , Sayani Ghosh , Hafizur Rahaman , Santanu Chattopadhyay

{"title":"Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs","authors":"Priyajit Mukherjee , Sayani Ghosh , Hafizur Rahaman , Santanu Chattopadhyay","doi":"10.1016/j.vlsi.2025.102534","DOIUrl":"10.1016/j.vlsi.2025.102534","url":null,"abstract":"<div><div>3D-Mesh NoCs containing hundreds of cores suffer from excessive traffic loads in the routers which often lead to the creation of thermal hotspots as well as severe routing congestion issues. The state-of-the-art deterministic routing techniques fail to balance this huge traffic loads due to their rigid path selection policy. On the other hand, adaptive routing techniques require additional temperature- and traffic-detection and management circuits as well as computation-intensive router architectures. Therefore, to harness the fundamental benefits of Network-on-Chip (NoC) architectures such as simplicity and scalability, this work implements a novel deterministic routing technique which efficiently adjusts the routing paths for a target application by adding a halt router in the path between the source and destination routers. A combination of Discrete Particle Swarm Optimization (DPSO) and Simulated Annealing (SA) algorithms have been used to optimally select the halt routers’ positions such that both the traffic load variance of the network and the peak temperature of the chip get reduced. Based on the offline positioning of halt routers a halted routing algorithm has been used to transfer the packets from source to halt router and then halt to destination router. PARSEC and SPLASH-2 benchmarks are used to generate the target traffic patterns. The experimental results show that the proposed halted routing strategy is able to produce significant reduction in both chip temperature (up to 10 °C) and traffic-load variance (up to 42%) when applied on the standard deterministic routing techniques - Thermal-aware Selective Detour (<span><math><mrow><mi>T</mi><mi>S</mi><mi>D</mi></mrow></math></span>), Downward-XYZ (<span><math><mrow><mi>D</mi><mi>R</mi></mrow></math></span>), <span><math><mrow><mi>X</mi><mi>Y</mi><mi>Z</mi></mrow></math></span>, and <span><math><mrow><mi>Z</mi><mi>X</mi><mi>Y</mi></mrow></math></span> routings.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102534"},"PeriodicalIF":2.5,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145097542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-agent based minimal-layer via routing algorithm for PCB design 基于多智能体的最小层布线算法的PCB设计

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-09-02 DOI: 10.1016/j.vlsi.2025.102533

Jianhao Cao , Hao Cai , Ning Xu

{"title":"Multi-agent based minimal-layer via routing algorithm for PCB design","authors":"Jianhao Cao , Hao Cai , Ning Xu","doi":"10.1016/j.vlsi.2025.102533","DOIUrl":"10.1016/j.vlsi.2025.102533","url":null,"abstract":"<div><div>In Electronic Design Automation (EDA), the automatic routing of Printed Circuit Boards (PCBs) is essential for improving design efficiency and enhancing product performance. As electronic devices continue to evolve towards higher performance and miniaturization, PCB design becomes increasingly complex. Developing algorithms that effectively address these intricate routing challenges under constraints has emerged as a focal point of research. This paper introduces, for the first time, the adaptation of the Conflict-Based Search (CBS) algorithm from Multi-Agent Path Finding (MAPF) to PCB routing within the EDA domain. We propose a new routing method, termed the Minimal Layer Via (MLV)-CBS method, which achieves minimal vias while enhancing routing quality and efficiency. This method extends the CBS algorithm from point-to-point to line-to-line and integrates it with existing PCB routing theories. Additionally, we have developed two new strategies to enhance the efficiency of large-scale PCB routing: adaptive heatmap partitioning and congestion-negotiated routing order. Through theoretical analysis and experimental validation, these strategies have been shown to reduce solution times and improve efficiency. Tests on open-source PCB datasets indicate that the MLV-CBS algorithm performs favorably compared to commercial software and other algorithms. These results also provide valuable insights for the automation of PCB routing.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102533"},"PeriodicalIF":2.5,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A survey on vertical interconnection and topology of three-dimensional network-on-chip 三维片上网络垂直互连与拓扑研究进展

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-08-29 DOI: 10.1016/j.vlsi.2025.102529

Yuan Zhang , Zewei Jing , Qinghai Yang , Nan Cheng , Huaxi Gu , Kyung Sup Kwak

{"title":"A survey on vertical interconnection and topology of three-dimensional network-on-chip","authors":"Yuan Zhang , Zewei Jing , Qinghai Yang , Nan Cheng , Huaxi Gu , Kyung Sup Kwak","doi":"10.1016/j.vlsi.2025.102529","DOIUrl":"10.1016/j.vlsi.2025.102529","url":null,"abstract":"<div><div>The three-dimensional network-on-chip (3D NoC) has been proposed with the continuous advancement of integrated circuits (ICs) to address the inherent limitations of conventional two-dimensional NoC (2D NoC) architectures. 3D NoCs introduce direct vertical inter-layer electrical connections, enabling the integration of additional processing elements (PEs) within a limited area, hence significantly enhancing integration density and communication efficiency. However, the performance and scalability of 3D NoCs are highly dependent on vertical interconnection technologies and topology designs. In this survey, we discuss the development of 2D and 3D IC/NoC, providing a comprehensive overview of various vertical interconnection technologies evolved from conventional bonding to through-via (especially through-silicon-via) and to contactless connection. Additionally, we categorize the topologies of 3D NoCs based on their shapes and compare their degree, diameter, connections, and bisection bandwidth. The current challenges and future research opportunities are discussed to provide a foundation for the continued advancement and development in 3D NoCs.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102529"},"PeriodicalIF":2.5,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145003690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems 基于改进误差补偿的对数平方根容错系统的低功耗硬件结构

IF 2.5 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-08-29 DOI: 10.1016/j.vlsi.2025.102522

Prateek Goyal, Sujit Kumar Sahoo

{"title":"Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems","authors":"Prateek Goyal, Sujit Kumar Sahoo","doi":"10.1016/j.vlsi.2025.102522","DOIUrl":"10.1016/j.vlsi.2025.102522","url":null,"abstract":"<div><div>Approximate computing optimizes arithmetic circuits by reducing power and resource usage for applications that tolerate some error, offering hardware advantages over traditional designs. A key component, the square rooter, is resource-intensive, especially in image and signal processing, making its optimization crucial. This work presents a low-power, resource-efficient optimized logarithmic square rooter (OLSR) that calculates the square root of a <span><math><mrow><mn>2</mn><mi>n</mi></mrow></math></span>-bit unsigned integer using addition and shift operations with minimal error. The proposed approximate square rooter outperforms the precise restoring array-based design by using 73% fewer resources, achieving a 53% faster operation, and delivering 81% better power savings. Despite some trade-offs in approximation error, the results are highly acceptable, with a normalized mean error distance (NMED) of <span><math><mrow><mn>1</mn><mo>.</mo><mn>08</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></math></span>, a mean relative error distance (MRED) of <span><math><mrow><mn>1</mn><mo>.</mo><mn>77</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup></mrow></math></span>, a mean error distance (MED) of 2.77, and a maximum error distance (ED<span><math><msub><mrow></mrow><mrow><mtext>max</mtext></mrow></msub></math></span>) of 11. This design balances efficiency and precision well. The design is implemented on an Artix-7 FPGA using Verilog-HDL and validated in Xilinx Vivado. Comparisons with four other approaches highlight the OLSR’s strong balance between accuracy and hardware efficiency, with outstanding performance in the Sobel edge detection and Image enhancement application.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102522"},"PeriodicalIF":2.5,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144921592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0