Integration-The Vlsi Journal最新文献

{"title":"Matching constraint extraction for analog integrated circuits layout via edge classify","authors":"Ran Ran Wu,&nbsp;Yong Zhang,&nbsp;Zhen Hua He,&nbsp;Bo Wen Jia,&nbsp;Ning Xu","doi":"10.1016/j.vlsi.2024.102239","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102239","url":null,"abstract":"<div><p>Achieving matching constraints between various components is important in analog integrated circuit (IC) layout design, as it can reduce the impact of layout parasitics on the performance of IC. When automating analog integrated circuit layout design, identifying accurate matching constraints is an essential step before placement and routing. The matching relationship between devices strongly depends on circuit's topology and design expertise. This work focuses on differential circuits with various topologies and proposes a supervised learning framework that incorporates symmetry analysis. The heterogeneous multi-relationship graph representation is proposed to capture circuit's topology and extract matching constraints. Additionally, a symmetry analysis algorithm and filtering method based on matching levels are investigated to enhance the model's performance. The experimental results demonstrate that this work maintains a low false alarm rate and outperforms other matching constraint detection algorithms in terms of F₁ score and accuracy.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141607572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and research of grounding current monitoring device for converter transformer core and clamp","authors":"Haonan Bai ,&nbsp;Guoxin Zhao ,&nbsp;Dezhi Chen ,&nbsp;Xiu Zhou ,&nbsp;Xiaofeng Zheng","doi":"10.1016/j.vlsi.2024.102238","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102238","url":null,"abstract":"<div><p>The effective monitoring of the grounding current of the core and clamp of the converter transformer can prevent partial overheating, gassing of oil, and other abnormal conditions caused by the grounding fault of the core and clamp, ensuring the safety and stability of the power system. At present, the main detection and diagnosis method is to use the clamp current meter to detect the effective value of the grounding current. However, due to the larger capacity, higher voltage level, more complex structure and electromagnetic field distribution of the converter transformer, there is no clear standard and detection diagnosis method. Firstly, this paper analyzes the causes of grounding current and related calculations. And the design of the monitoring system for the grounding current of the converter transformer core and clamp design of the hardware system for the grounding current of the converter transformer is studied and the design process of the main circuit is given. Secondly, aiming at the problem of amplitude measurement deviation and non-integer frequency of harmonic generated by the grounding current of the core and clamp, a harmonic current detection and analysis scheme based on four Blackman-harris algorithms and the specific design process are proposed. Third, a diagnostic method based on probabilistic neural network is proposed, and a software platform is built to display and diagnose the grounding current state according to it. Finally, a prototype was manufactured and experimental study was carried out to verify the correctness of the proposed scheme.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141595751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic","authors":"Chua-Chin Wang,&nbsp;L S S Pavan Kumar Chodisetti,&nbsp;Durga Srikanth Kamarajugadda,&nbsp;Oliver Lexter July Alvarez Jose,&nbsp;Pradyumna Vellanki","doi":"10.1016/j.vlsi.2024.102234","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102234","url":null,"abstract":"<div><p>Adders are critical to the efficiency of arithmetic circuits in battery-powered electronic devices. This study demonstrates an 8-bit CLA (carry look-ahead adder) using single-phase ANT logic to increase the computation speed and reduce the power dissipation simultaneously. The single-phase ANT has no internal loop that optimizes the efficiency of the prior ANT. Utilizing a TSMC 40-nm technology, the proposed 8-bit CLA is fabricated. It attains the highest operating frequency of 3.2 GHz and the lowest normalized PDP (power delay product) by on-silicon measurement for 20 pF load.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141595750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-based control system for real-time driving of UHD Micro-LED display with color calibration","authors":"Tsung-Han Tsai,&nbsp;Shang-Wei Lin","doi":"10.1016/j.vlsi.2024.102237","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102237","url":null,"abstract":"<div><p>Micro-LED technology offers numerous advantages, including high brightness, low power consumption, and superior color performance. However, driving micro LED displays requires complex control algorithms and high-speed data processing. To address these challenges, this paper presents the development of a real-time FPGA-based control system for a 68-inch 4K/60Hz micro-LED display. The objective of this project was to create a high-performance control system capable of driving the micro-LED display with precise color accuracy, supporting 10-bit color depth for enhanced color rendition. One crucial aspect of the system is color calibration, which ensures accurate color reproduction across the display, maintaining consistent and vibrant colors. By incorporating advanced color calibration techniques, the system achieves excellent color consistency and fidelity, providing a visually stunning viewing experience. Moreover, the system incorporates hot plug functionality, allowing for seamless reconnection of the display after Ethernet disconnection. This feature ensures uninterrupted operation and enhances user experience. In FPGA design, the proposed system demonstrates the feasibility and effectiveness of real-time control in driving micro-LED displays, offering improved color performance and reliable operation in various applications.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141542561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and application of multiscroll chaotic attractors based on memristors","authors":"Jie Zhang,&nbsp;Xiaodong Wei,&nbsp;Jiangang Zuo,&nbsp;Nana Cheng,&nbsp;Jiliang Lv","doi":"10.1016/j.vlsi.2024.102235","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102235","url":null,"abstract":"<div><p>A multi-segment nonlinear memristor model with controllable parameters is simplified significantly reducing circuit costs without compromising circuit performance. Different quantities of simplified memristor models are introduced into an improved Shimizu and Morioka (S-M) system, which constitute the one-directional memristive multiscroll chaotic attractor (1D-MMSCA) and the two-directional memristive multiscroll chaotic attractor (2D-MMSCA). Dynamical analysis is conducted from equilibrium points, Lyapunov exponents and bifurcation diagrams, Poincaré map, 0–1 tests, complexity, coexisting attractors, and National Institute of Standards and Technology (NIST) test. The Lyapunov exponents and bifurcation diagrams revealed that 1D-MMSCA exhibit rich dynamical behaviors, including fixed points, periodic orbits, transient quasi-periodic cycles, limit cycles, and period-doubling bifurcations. The 2D-MMSCA demonstrates simultaneous homogeneous and heterogeneous multi-stability and extreme multi-stability. Furthermore, an analog circuit is designed and simulated, and the results verify the circuit realizability and correctness of the MMSCAs. By utilizing an improved Euler algorithm and STM32 microcontroller, the implementation of MMSCAs are achieved, enhancing their applicability in the embedded systems domain. Finally, the drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. This significantly expands the application scope of the system. Additionally, a chaotic analog encrypted communication system has been developed using this synchronization framework. These advancements substantially enhance both the efficiency and practicality of the synchronization system.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141480127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra8T: A sub-threshold 8T SRAM with leakage detection","authors":"Shan Shen ,&nbsp;Hao Xu ,&nbsp;Yongliang Zhou ,&nbsp;Ming Ling ,&nbsp;Wenjian Yu","doi":"10.1016/j.vlsi.2024.102233","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102233","url":null,"abstract":"<div><p>In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>D</mi><mi>D</mi><mi>M</mi><mi>I</mi><mi>N</mi></mrow></msub></math></span>). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>D</mi><mi>D</mi><mi>M</mi><mi>I</mi><mi>N</mi></mrow></msub></math></span> by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 <span><math><mi>μ</mi></math></span>s read delay, and the minimum energy required is 1.69 pJ at 0.4 V</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141542560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model","authors":"Janaki K ,&nbsp;Srinivasan C ,&nbsp;Hema Malini A","doi":"10.1016/j.vlsi.2024.102231","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102231","url":null,"abstract":"<div><p>In an era dominated by technology, the imperative for robust personal authentication in electronic information systems becomes increasingly evident. A secure and dependable solution to address this need is biometric authentication. Due to their intrinsic features of being universal, unique, and fraud-resistant, finger vein-based recognition systems have gained importance. Veins provide an efficient barrier against misleading methods since they are buried under the skin and undetectable to human sight. While many researchers focus on advanced technology for finger-vein-based authentication systems, existing research has often overlooked significant challenges, such as short datasets, high computational complexity, and a lack of efficient and lightweight feature descriptors. This paper proposes a unique method for automated Finger Vein Recognition (FVR) based on a fusion model known as “CNN-ViT” for FVR. Transfer learning-based Convolutional Neural Network (CNN) models, such as Inception-V3 and ResNet-50, compute the correlation of adjacent pixels to process texture-based features. Furthermore, shape-based features are processed using the vision transformer (ViT) model to determine the relationship between distant pixels. The combination of these three models enables the learning of textural features based on forms, contributing to more effective finger vein identification. In addition to our databases, we utilize two benchmark databases, FV-USM and SDUMLA-HMT, to validate our experiments. Our proposed approach achieves outstanding accuracy values of 99.95 %, 98.9 %, and 97.78 % on both the benchmark and our datasets. When compared to previous methods, the proposed Deep Learning (DL) model outperforms state-of-the-art models, demonstrating higher recognition rates and accuracy. To prototype the proposed FVR system, a Zynq XCZU4EV UltraScale + Multiprocessor System-On-Chip (MPSoC) was employed. The proposed model exhibits high throughput and competitive power efficiency, making it an excellent choice for scenarios where computing performance is critical, albeit utilizing more power and resources. This was established through a comprehensive examination of FPGA resource utilization and performance metrics.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141438000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications","authors":"Hyeon-June Kim","doi":"10.1016/j.vlsi.2024.102232","DOIUrl":"10.1016/j.vlsi.2024.102232","url":null,"abstract":"<div><p>This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141391393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues","authors":"Dharmaray Nedalgi ,&nbsp;Saroja V. Siddamal ,&nbsp;S.S. Kerur","doi":"10.1016/j.vlsi.2024.102230","DOIUrl":"10.1016/j.vlsi.2024.102230","url":null,"abstract":"<div><p>This paper presents circuit for <span><math><mrow><mn>2</mn><mo>×</mo><mtext>VDD</mtext></mrow></math></span> signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for <span><math><mrow><mn>2</mn><mo>×</mo><mtext>VDD</mtext></mrow></math></span> signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141397583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A pseudo resistor with temperature self-adaptive scheme","authors":"Aliaa Mohamed Salem ,&nbsp;Ahmed Wahba ,&nbsp;Hesham F.A. Hamed ,&nbsp;Ahmed Reda Mohamed","doi":"10.1016/j.vlsi.2024.102229","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102229","url":null,"abstract":"<div><p>A temperature self-adaptive ultra-high-resistance pseudo-resistor (PR) circuit is proposed for a wide range of biomedical applications. It acts as a relatively constant resistor over a wide temperature range (−40 °C–85 °C) due to its potential to compensate for the impact of the temperature-induced current. Hence, the performance of many biomedical analog intellectual property (IP) circuits can be effectively improved with temperature variations. The proposed circuit consists of a gate-voltage-controlled pseudo-resistor and a proportional-to- absolute-temperature (PTAT) circuit. Besides, its analysis and proof of concept with the self-adaptive scheme are presented. The circuit is designed in standard 0.18 μm CMOS technology and occupies a silicon area of 18.5 × 43.7 μm². It consumes 12 nW with a single power supply of 1.8 V. The post-layout simulation results demonstrate that the proposed pseudo-resistor could adequately improve the temperature-induced resistance variation by up to 18X while consuming ultra-low power and providing relatively high-temperature independence compared to the prior art.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141313946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}