Integration-The Vlsi Journal最新文献_第4页

A wide-output buck DC-DC power management IC 宽输出降压型 DC-DC 电源管理集成电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-06 DOI: 10.1016/j.vlsi.2024.102278

Xinglong Guo , Qingqing Wu , Yanhang Du , Xinyu Li , Zihao Cui

{"title":"A wide-output buck DC-DC power management IC","authors":"Xinglong Guo , Qingqing Wu , Yanhang Du , Xinyu Li , Zihao Cui","doi":"10.1016/j.vlsi.2024.102278","DOIUrl":"10.1016/j.vlsi.2024.102278","url":null,"abstract":"<div><p>-This article designs and develops a wide-input voltage, high-efficiency, small-size, and peak current-mode control step-down DC-DC converter. The Cadence Spectre simulation tool is used for system simulation to verify the performance of the chip. The overall research content of the article includes the function of the output under heavy load, light load and the stability of the output under transient load changes. The specific content of the research is buck synchronous step-down DC-DC converter chip with pulse modulated. It is provided with an input-voltage range of 6 V–80 V and maximum output-voltage range 72 V. The chip possesses wide operating temperature range of −20 °C to 130 °C. The 92 % high-efficiency can be achieved by using a PWM/PFM hybrid modulation method. When achieving transient load jump, the output voltage change shall not exceed 150 mV. The maximum load current of the chip is 1 A. Furthermore, the chip is packaged and samples can be obtained, and the output light load/heavy load, and other functions are tested through the circuit board. In addition, the chip achieved tape out by using 0.18 μm CMOS process with size of 2027 μm <span><math><mrow><mo>×</mo></mrow></math></span> 2020 μm. The converter features current mode control to simplify external compensation and optimize transient response through a wide range of inductors and output capacitors. It can be adopted user-programmable soft-start time to prevent inrush current during startup. It also includes thermal shutdown protection to provide safe and smooth operation in operating conditions.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102278"},"PeriodicalIF":2.2,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142164178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LA-ring based non-linear components: Application to image security 基于 LA 环的非线性组件：图像安全应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-05 DOI: 10.1016/j.vlsi.2024.102279

Nazli Sanam, Summiya Mumtaz, Samreen Khalid

{"title":"LA-ring based non-linear components: Application to image security","authors":"Nazli Sanam, Summiya Mumtaz, Samreen Khalid","doi":"10.1016/j.vlsi.2024.102279","DOIUrl":"10.1016/j.vlsi.2024.102279","url":null,"abstract":"<div><p>The prevalent utilization of symmetric block ciphers in contemporary information security systems reinforces the need for immediate action to increase their effectiveness. This task is considered crucial in the synthesis of high-quality cryptographic primitives, particularly S-boxes. In accordance with this requirement, the current article demonstrates a strategy for generating an 8 × 8 S-box drawing over an LA-ring of order 1024, which is considered a substantial class of non-associative rings. For the purpose of investigating LA-ring and their practical uses, it is essential to have illustrative examples. However, obtaining such examples using current methods is tedious and yields limited results. Therefore, this research explores an intriguing opportunity for an extensive exploration of LA-ring, far exceeding the limitations previously established and offering a valuable analytical approach for creating examples of higher-order LA-ring by drawing upon lower orders. The manuscript also performs a variety of standard evaluation tests based on five core indicators, which highlight their potential as parallels to the existing frameworks. By using the crafted S-box, an image encryption approach is launched that aims to enhance security measures. It is therefore seen that the recommended S-box has shown a high potential for causing confusion during the substitution phase, and a 3D chaotic map is implemented for the pixel permutation in order to create diffusion into the colour image. Certainly, the discovery is leading to a foundational framework among academics and is expected to serve as the basis for numerous implementations in the future.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102279"},"PeriodicalIF":2.2,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142242433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 3D-stack DRAM-based PNM architecture design 基于 3D 堆栈 DRAM 的 PNM 架构设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-09-02 DOI: 10.1016/j.vlsi.2024.102266

Qiang Zhou , Bing Wang , XinTing Xiao

引用次数: 0

Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications 用于短程高速毫米波和太赫兹通信的集成电子硅互连器件

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-31 DOI: 10.1016/j.vlsi.2024.102267

Zhihong Lin , Shiqi Chen , Yuan Liang , Lin Peng

{"title":"Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications","authors":"Zhihong Lin , Shiqi Chen , Yuan Liang , Lin Peng","doi":"10.1016/j.vlsi.2024.102267","DOIUrl":"10.1016/j.vlsi.2024.102267","url":null,"abstract":"<div><p>—Millimeter-wave and terahertz interconnects implemented in advanced complementary metal oxide semiconductor (CMOS) technologies have emerged as promising solutions to fix the issues encountered by baseband interconnects and optical interconnects across specific communication ranges. Over the last decade, significant attempts to advance millimeter-wave and terahertz electronics and platforms have been made. Notably, there have been ground-breaking advancements in active components, including modulation techniques, low-noise receivers, efficient and high-output-power signal generators, and high-frequency clock synthesizers. Nevertheless, since energy efficiency is of paramount importance for interconnect applications, it is necessary to prioritize efficiency enhancements over improvements in signal power, signal integrity and noise related performance. Strategies to improve system output power and phase noise as well as strategies to reduce channel loss and channel electromagnetic crosstalk should leverage alternative approaches, such as architectural optimizations and array configurations, rather than prioritizing energy efficiency. As such, the progression of passive channel technology is equally vital. While reducing channel insertion loss is essential for extending communication reach, channel dispersion and crosstalk limitations at the interface level present critical challenges to achieving optimal bandwidth over distances of up to a few meters. This underscores the need for a balanced focus on both active and passive component innovations to fully harness the potential of millimeter-wave and terahertz interconnects in overcoming the limitations of current CMOS technologies.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102267"},"PeriodicalIF":2.2,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142228524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An analytical placement algorithm with looking-ahead routing topology optimization 具有前瞻性路由拓扑优化功能的分析放置算法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-31 DOI: 10.1016/j.vlsi.2024.102264

Min Wei , Xingyu Tong , Zhijie Cai , Peng Zou , Zhifeng Lin , Jianli Chen

{"title":"An analytical placement algorithm with looking-ahead routing topology optimization","authors":"Min Wei , Xingyu Tong , Zhijie Cai , Peng Zou , Zhifeng Lin , Jianli Chen","doi":"10.1016/j.vlsi.2024.102264","DOIUrl":"10.1016/j.vlsi.2024.102264","url":null,"abstract":"<div><p>Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer. On industrial benchmarks, our algorithm can also achieve a 10.6% improvement in routing wirelength, 27.3% in WNS, and 34.4% in TNS.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102264"},"PeriodicalIF":2.2,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142150576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A three-stage single-miller CMOS OTA with no lower load capacitor limit 无负载电容下限的三级单填充 CMOS OTA

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-30 DOI: 10.1016/j.vlsi.2024.102269

P. Manikandan

引用次数: 0

A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ √(H z) noise and 190.47 nW micro-power for ECG applications 用于心电图应用的新型可调电容表列仪表放大器，噪声为 14.4 nV/√（H z），微功率为 190.47 nW

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-30 DOI: 10.1016/j.vlsi.2024.102268

Sujeet Kumar Gupta , Riyaz Ahmad , Dharmendar Boolchandani , Sougata Kumar Kar

{"title":"A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ √(H z) noise and 190.47 nW micro-power for ECG applications","authors":"Sujeet Kumar Gupta , Riyaz Ahmad , Dharmendar Boolchandani , Sougata Kumar Kar","doi":"10.1016/j.vlsi.2024.102268","DOIUrl":"10.1016/j.vlsi.2024.102268","url":null,"abstract":"<div><p>This paper describes a low-power, low-noise capacitively-coupled instrumentation amplifier (CCIA) designed for capturing biopotential signals. The main advantage of proposed design are as (i) CCIA based on new IA has been proposed, (ii) the lower cutoff frequency has been improved by adding MOS based resistor, (iii) g<sub>m</sub> enhancement circuit is added in operational transconductance amplifier (OTA) based fully differential difference amplifier (FDDA)to improve gain and bandwidth. The DC electrode-offset voltage is reduced and the input impedance is increased by using feedback mechanism. Cadence EDA tool is used to analyze the findings of the proposed CCIA's in 0.18 μm, CMOS technology with a 1.8 V power supply. The proposed CCIA architecture has an adjustable mid-band gain from 52.55 to 61.11 dB for bias voltage ranges from 0.1 to 0.6 V, frequency range of 0.06 Hz–1.72 kHz, and a CMRR of 122 dB. The proposed CCIA has a total power dissipation of 190.47 nW and equivalent input referred noise (IRN) of 14.4 nV/sqrtHz at 0.01 Hz. It only occupies 0.01 mm<sup>2</sup> of core area. To assess the robustness of suggested design, PVT analysis, post layout simulation and a comparison with previously published works demonstrates the competence of the design.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102268"},"PeriodicalIF":2.2,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142128398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications 用于提高毫米波应用 CMOS 射频集成电路面积效率的不规则八边形片上电感器实验分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-24 DOI: 10.1016/j.vlsi.2024.102259

Subbareddy Chavva, Immanuel Raja

{"title":"Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications","authors":"Subbareddy Chavva, Immanuel Raja","doi":"10.1016/j.vlsi.2024.102259","DOIUrl":"10.1016/j.vlsi.2024.102259","url":null,"abstract":"<div><p>This article deals with the analysis of irregularly shaped single turn octagonal spiral inductors for millimeter-wave and sub-THz CMOS IC designs. Simulations and experimental results, along with theoretical formulations, are used to characterize these irregular structures. This article proposes a novel approach for efficient use of silicon chip area by reshaping the on-chip inductors used in millimeter wave (mm-wave) applications without compromising the performance of the inductors. Especially in CMOS RFICs when a space constraint exists in either <span><math><mi>X</mi></math></span>- or <span><math><mi>Y</mi></math></span>-direction in their layout, such reshaping can be attempted. Moreover, two novel methods of reshaping the inductors are proposed and studied thoroughly. The study of these irregular shapes has interesting conclusions, which are validated through on-wafer measurements. Certain methods of reshaping result in inductors which do not have degradation in their quality factors (<span><math><mi>Q</mi></math></span>), while other approaches degrade the <span><math><mi>Q</mi></math></span>. Based on these insights, a design methodology is proposed for designers who need to reshape their inductors to irregular structures while not compromising on the quality factor. The measurement results agree with the simulations and prove that the proposed reshaping is practically possible.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102259"},"PeriodicalIF":2.2,"publicationDate":"2024-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow 使用嵌入 DFT 流程的专用 Pure MaxSAT 求解器的快速测试压实方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-22 DOI: 10.1016/j.vlsi.2024.102265

Zhiteng Chao , Xindi Zhang , Junying Huang , Zizhen Liu , Yixuan Zhao , Jing Ye , Shaowei Cai , Huawei Li , Xiaowei Li

{"title":"A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow","authors":"Zhiteng Chao , Xindi Zhang , Junying Huang , Zizhen Liu , Yixuan Zhao , Jing Ye , Shaowei Cai , Huawei Li , Xiaowei Li","doi":"10.1016/j.vlsi.2024.102265","DOIUrl":"10.1016/j.vlsi.2024.102265","url":null,"abstract":"<div><p>Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary to sharply reduce time and memory overhead, and leverages a dedicated Pure MaxSAT solver to re-compact the test patterns generated by ATPG tools. We also observe that ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficiency. In our experiments conducted on benchmark circuits ISCAS89, ITC99, and an open-source RISC-V CPU, we employed two methodologies. For commercial tool, we utilized a non-intrusive approach, while we adopted an intrusive method for open-source ATPG. Under the non-intrusive approach, our method achieved a maximum reduction of 34.69% in pattern count and a maximum 29.80% decrease in test cycles as evaluated by a leading commercial tool. Meanwhile, under the intrusive approach, our method attained a maximum 71.90% reduction in pattern count as evaluated by an open-source ATPG tool. Notably, fault coverage remained unchanged throughout the experiments. Furthermore, our approach demonstrates improved performance compared with existing methods.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"100 ","pages":"Article 102265"},"PeriodicalIF":2.2,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Clock mesh synthesis through dynamic programming with physical parameters consideration 通过考虑物理参数的动态编程合成时钟网格

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-08-19 DOI: 10.1016/j.vlsi.2024.102261

Dejian Li , Jie Gan , Chongfei Shen , Qi Chen , Lixin Yang , Sihai Qiu , Xin Jin , Tiantian Wu , Zhijie Chen , Meng Liu

引用次数: 0