Integration-The Vlsi Journal最新文献

{"title":"Side-channel attack resilient implementation of homomorphic encryption using elliptic curve cryptography for secure cloud computing","authors":"Parthasarathy R.,&nbsp;Saravanan P.","doi":"10.1016/j.vlsi.2025.102439","DOIUrl":"10.1016/j.vlsi.2025.102439","url":null,"abstract":"<div><div>In recent times, the amount of data exchanged between the cloud storage and the users has proliferated. The security of that data is also critical. To secure that data and to enhance its integrity, it should be encrypted before being uploaded into the cloud. In this work, a side-channel attack-secured additive homomorphic encryption is implemented using elliptic curve cryptography on an FPGA platform. An elliptic curve scalar multiplication, which is the critical component of elliptic curve cryptography, is designed in the general prime field using standard projective coordinate representation and implemented for 192, 224, and 256 bits as per the left-to-right double-and-add algorithm using radix-4 Booth-encoded modular multipliers in both FPGA devices and the ASIC platform. A minimum of 8242 slices is required to implement the proposed 256-bit elliptic curve scalar multiplication in the Virtex-6 FPGA device. The area of the proposed 192, 224, and 256-bit elliptic curve scalar multiplication is estimated as 149.225K, 208.178K, and 266.981 KGE in the ASIC using Cadence gpdk-45 nm technology libraries. A correlation power analysis attack is mounted on the FPGA implementation of the proposed elliptic curve scalar multiplication with an 8-bit data size to determine the value of scalar ‘n’. The attack is successful with a minimum of 2301 traces, and a high correlation coefficient value is obtained. Scalar randomization is proposed and integrated with the design as a countermeasure part to thwart the correlation power analysis attack, which is successful, and hence the left-to-right double-and-add algorithm used to determine elliptic curve scalar multiplication is made secure against side-channel attacks. This secured hardware implementation of elliptic curve cryptography is utilized to encrypt the data uploaded to the cloud, where additive homomorphic encryption is employed to process the data. Hence, additive homomorphic encryption becomes side-channel attack resilient, and cloud computations are secured.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102439"},"PeriodicalIF":2.2,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memory device based on memristor-diode crossbar and control CMOS logic for spiking neural network hardware","authors":"A.N. Busygin ,&nbsp;A.D. Pisarev ,&nbsp;S. Yu Udovichenko ,&nbsp;A.H.A. Ebrahim","doi":"10.1016/j.vlsi.2025.102461","DOIUrl":"10.1016/j.vlsi.2025.102461","url":null,"abstract":"<div><div>A compact electrical circuit of a memory device based on a memristor-diode crossbar array and peripheral CMOS control logic has been developed. The peripheral logic circuit is digitally controlled and allows reading and changing the state of individual memristors. This functionality is necessary to store and transfer the synaptic states of the neural network to another neural network to avoid re-learning. Simple original electrical circuits of input and output drivers utilizing standard rectangular impulses to control memristor-diode crossbar were created. These circuits ensure the operation of the memristor matrix both as part of the hardware spiking neural network and in the modes of writing and reading the state of the memristors. Exclusion of multiple DACs and ADCs in the electrical circuits of input and output crossbar conductor drivers made it possible to significantly reduce the occupied area on the chip. On the basis of numerical modeling using the experimental characteristics of memristors the maximum size of crossbar in the developed circuit and the influence of parasitic currents on the processes of writing and reading the state of memristors are estimated. Connection of the peripheral logic circuit in the memristor leads to a limitation of the maximum size of the crossbar due to additional parasitic currents. A method of compensating the influence of parasitic currents on the process of setting memristors in a given state by varying the duration of programming pulses is proposed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102461"},"PeriodicalIF":2.2,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144240834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A lightweight general PUF framework for resisting machine learning attacks","authors":"Tianming Ni ,&nbsp;Fei Li ,&nbsp;Zhengfeng Huang ,&nbsp;Aibin Yan ,&nbsp;Senling Wang ,&nbsp;Xiaoqing Wen ,&nbsp;Mu Nie ,&nbsp;Jingchang Bian","doi":"10.1016/j.vlsi.2025.102459","DOIUrl":"10.1016/j.vlsi.2025.102459","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF) is an attractive and low-cost security primitive that requires no storage and is resistant to reverse engineering. However, classical PUFs are highly vulnerable to machine learning attacks, and most attempts to resist these attacks consume excessive resources. To address this challenge, a lightweight general PUF framework is proposed in this paper. Firstly, the framework adopts segmentation processing to introduce structural nonlinearities for the purpose of self-protection. Secondly, the pre-segment response, pre-segment challenges and post-segment challenges undergo XOR processing to introduce challenges obfuscation, which greatly enhances the machine learning resistance of the PUF. In addition, for configurable RO PUF, a novel MUX-based RO (called MRO) is proposed in this paper, which can save resources by 50 %. Implementing a two-segment MRO-MRO instance based on the proposed PUF framework results in reliability, uniformity, and uniqueness that are close to the ideal values. Comprehensive experiments demonstrate that the proposed PUF has the advantages of scalable framework, low resource overhead, and strong resistance to machine learning attacks.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102459"},"PeriodicalIF":2.2,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144240832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hierarchical rotated binary placement for nonlinearity reduction in digital-to-analog converters","authors":"Mikhail M. Pilipko,&nbsp;Mikhail S. Yenuchenko","doi":"10.1016/j.vlsi.2025.102457","DOIUrl":"10.1016/j.vlsi.2025.102457","url":null,"abstract":"<div><div>A capacitive digital-to-analog converter (DAC) is a key component in analog-to-digital converters of various types. Such DACs contain an array of capacitors that is affected by components mismatch appearing during integrated circuit production.</div><div>Placement schemes are an effective solution to mitigate the influence of systematic mismatch on linearity of data conversion. Previously known placement schemes have some weak points concerning the bit placement, e.g. anisotropy.</div><div>In order to overcome these drawbacks, an algorithm for the Hierarchical Rotated Binary Placement (HRBP) is proposed in this paper. This placement scheme suits even and odd resolutions. Over the range of 4–10 bits, it provides a linearity improvement of 3–69 % relative to other solutions. Extended evaluation methods confirm this improvement. A systematic approach for wire routing, regardless of a resolution, is also proposed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102457"},"PeriodicalIF":2.2,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A lightweight FPGA accelerator for onboard processing of hyperspectral anomaly detection based on optimized TinyYOLOv3 model","authors":"D. Venkat Reddy ,&nbsp;M.V. Nageswara Rao ,&nbsp;T.V.V. Satyanarayana ,&nbsp;T. Aravinda Babu ,&nbsp;Karna Vishnu Vardhana Reddy","doi":"10.1016/j.vlsi.2025.102443","DOIUrl":"10.1016/j.vlsi.2025.102443","url":null,"abstract":"<div><div>Due to the abundance and richness of spectral-spatial information, hyperspectral images (HSIs) obtained from hyperspectral imaging have been widely used in a variety of applications, including target or anomaly identification. However, due to its low processing complexity, onboard real-time anomaly identification has always been challenging in hyperspectral image analysis. To achieve high detection accuracy, most existing anomaly detection systems inevitably compromise on high computational complexity. In this paper, a new lightweight field-programmable gate array (FPGA) accelerator is proposed for hyperspectral anomaly detection using HSIs. The proposed approach consists of two stages. In the first stage, average fusion is used to reduce the dimensions of the HSIs. In the second stage, an optimized TinyYOLOv3 accelerator is utilized to extract features and detect anomalies. This optimized TinyYOLOv3 accelerator uses a hardware-friendly shift-based floating-fixed multiply accumulator (MAC) operator and a shift-based quantization method. The shift-based floating-fixed MAC operator is further optimized using a compact LUT-based multiplier (C-LUT-MUL) and an effective floating point adder. The proposed lightweight FPGA Accelerator is implemented on the coding tool Xilinx Verilog using San Diego, Urban-Beach, and EI Segundo datasets. The evaluation results reveal that the proposed accelerator has a higher resource consumption and processing speed (62.5 FPS) while maintaining maximum detection accuracy. This shows the benefits of the proposed lightweight FPGA accelerator over existing research.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102443"},"PeriodicalIF":2.2,"publicationDate":"2025-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144271256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamics analysis, FPGA implementation, and application in image encryption of a quadruple-wing chaotic system based on hyperbolic sine functions","authors":"Jie Zhang,&nbsp;Nana Cheng,&nbsp;Pengyuan Wang","doi":"10.1016/j.vlsi.2025.102437","DOIUrl":"10.1016/j.vlsi.2025.102437","url":null,"abstract":"<div><div>In this paper, a new fourth-order chaotic system based on hyperbolic sinusoidal functions is proposed. Numerical analysis methods such as the Lyapunov exponential, bifurcation diagram, and complexity test verify that this system has a new topology with multi-wing symmetry, and properties such as multiple stability, transient chaos, and bursting oscillations are observed, which demonstrates its rich dynamical behavior. Through the construction of hardware circuits and the implementation of Field Programmable Gate Array(FPGA), this system is proven to be realizable. The complexity of the system at different initial values is calculated and compared using the SE algorithm, and it is found that the proposed system has high sensitivity and stability, which makes it more suitable to be used for confidential communication. Finally, it is found that the new system, which combines multi-directional pixel misalignment and DNA dynamic encryption for image encryption of chaotic sequences, performs well in terms of robustness and information entropy.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102437"},"PeriodicalIF":2.2,"publicationDate":"2025-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144204874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced fault detection and localization in cross-referencing digital micro-fluidic biochips","authors":"Sagarika Chowdhury ,&nbsp;Debasish Dhal ,&nbsp;Rajat Kumar Pal ,&nbsp;Goutam Saha","doi":"10.1016/j.vlsi.2025.102440","DOIUrl":"10.1016/j.vlsi.2025.102440","url":null,"abstract":"<div><div>Cross-referencing digital microfluidic biochips (DMFBs) is becoming increasingly appealing as it significantly reduces the design's pin count. However, routing multiple droplets simultaneously within this architecture presents a challenging task. As a result, detecting multiple faulty electrodes within this setup has gained more attention. This paper introduces an advanced and rigorous offline testing technique that addresses the challenges of electrode interference and dynamic fluidic constraints. Given the need to manage multiple droplets simultaneously throughout the testing process, our approach meticulously considers every fine detail. We account for the time taken to reach pseudo-sources from the source, and from the pseudo-sinks to the sink, in addition to the actual travel time. Testing simulations have been conducted on various 2D grid sizes, with results showing a significant improvement in total detection time compared to some existing methods. This proposed technique successfully overcomes several limitations that previous works encountered.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102440"},"PeriodicalIF":2.2,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144222549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance","authors":"Komal Duggal ,&nbsp;Rishikesh Pandey ,&nbsp;Vandana Niranjan","doi":"10.1016/j.vlsi.2025.102442","DOIUrl":"10.1016/j.vlsi.2025.102442","url":null,"abstract":"<div><div>This paper presents a robust CMOS voltage reference optimized for automotive applications, where reliability is crucial under varying environmental and operational conditions. The proposed design ensures high accuracy and stability across a wide range of process, voltage, and temperature (PVT) variations, which are typical in automotive environments<strong>.</strong> The proposed voltage reference uses two current generators exhibiting similar temperature characteristics to attain a low-temperature coefficient and low line sensitivity across a wide temperature range. By subtracting these two similar behavior currents to eliminate temperature-induced variations and applying the difference to a diode-connected NMOS transistor, the design ensures stability against temperature and supply variations. A trimming circuit is employed to calibrate the temperature sensitivity and reference voltage across various process corners to achieve consistent PVT stability under all conditions. The proposed voltage reference is designed and simulated using 180 nm CMOS technology. The simulation outcomes demonstrate that the reference voltage is 458.24 mV for a 1.2–5V supply voltage range with 0.027 %/V line sensitivity. The temperature coefficient is 19.83 ppm/°C for −40 °C–180 °C temperatures. The power supply rejection ratio is −72.36 dB at 1 KHz and −72.17 dB at 10 KHz. Furthermore, the output noise is 0.6μV/√Hz at 1 KHz and 0.18μV/√Hz at 10 KHz. The circuit consumes 8.7 μW of power and occupies a minimal area of 0.0011 mm².</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102442"},"PeriodicalIF":2.2,"publicationDate":"2025-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144194601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Battery lifetime prediction considering domain-variate error","authors":"Ting Lu ,&nbsp;Wuyan Deng ,&nbsp;Guohua Liu ,&nbsp;Xiaoang Zhai ,&nbsp;Chenlong Yu ,&nbsp;Jiayu Wan ,&nbsp;Yang Liu ,&nbsp;Xin Li","doi":"10.1016/j.vlsi.2025.102438","DOIUrl":"10.1016/j.vlsi.2025.102438","url":null,"abstract":"<div><div>—With the rapid development of rechargeable battery technology, battery lifespan prediction has become a hot topic in current research. Data-driven models, due to their superior performance, have been widely applied in the field of battery lifespan prediction. These methods construct regression models by extracting features from early-cycle battery data to achieve accurate prediction of remaining useful life. However, non-ideal factors in real-world operating environments inevitably introduce noise interference into the raw battery datasets, and directly using noisy data for modeling significantly reduces prediction accuracy. To address this issue, the study proposes a noise-aware battery lifespan prediction framework based on modal decomposition. This framework employs a fully adaptive modal decomposition algorithm to decompose the original dataset, effectively removing noise components, and uses the high-quality derived features generated through interaction as inputs for the prediction model. Experimental validation on standard datasets demonstrates the framework's excellent predictive performance. To further evaluate the model's robustness, the study also conducted comparative experiments using a second dataset with added noise. The results show that, compared to traditional methods, the proposed approach exhibits significant noise reduction effects and notable improvements in prediction accuracy and stability, providing an effective solution for battery lifespan prediction.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102438"},"PeriodicalIF":2.2,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144139379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extended-chip-on-board (e-COB) heterogeneous integration of LEDs with LED drivers","authors":"H. Lyu,&nbsp;Y.F. Cheung,&nbsp;H.W. Choi","doi":"10.1016/j.vlsi.2025.102431","DOIUrl":"10.1016/j.vlsi.2025.102431","url":null,"abstract":"<div><div>In a conventional chip-on-board (COB) LED circuit, multiple LED dies are mounted on a common platform to achieve dense LED integration, improved heat-sinking, and lower production costs. Nevertheless, the COB LED is still driven by a conventional power supply. In this work, the extended-chip-on-board (e-COB) LED lighting system is proposed, whereby apart from the LEDs, the electronic driving circuit is also integrated into the same platform. Integration with both the linear regulated power supply (LRPS) and switch-mode power supply (SMPS) are explored. The result of such integration is a reduction in circuit footprint, which is more pronounced in the LRPS systems than the SMPS system due to its necessity for bulky inductors. For the LRPS systems, a fourfold reduction in footprint has been demonstrated, for an e-COB circuit comprising 10 LEDs in an annular arrangement. The e-COB system also operates cooler by <span><math><mrow><mo>∼</mo><mn>12</mn><mo>.</mo><mn>4</mn><mtext>%</mtext></mrow></math></span> at the driving voltage of 5 V, due to the direct thermal pathway between the heat source (LED, IC, etc.) to the heat sink (PCB), without having to route through the package. The e-COB packaging approach represents a solution for taking LED lighting system efficiency and compactness to the next level, which can readily be extended to non-lighting systems, especially where electrical and thermal efficiency is valued.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102431"},"PeriodicalIF":2.2,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}