Shutong Zhang , Pengjun Wang , Mengfan Xv , Bo Chen , Yuejun Zhang
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引用次数: 0
Abstract
Industrial Internet of Things (IoT) edge nodes urgently need encryption schemes that take into account key stability and hardware efficiency under low-power consumption and harsh working conditions, but existing technologies are limited by defects such as high key BER, high hardware resource overhead, and insufficient data security. To solve these problems, this paper proposes a four-mode reconfigurable in-situ memory unit, which accomplishes the hardware multiplexing of key generation, dynamic screening, heterodyne encryption and dense state storage functions, and combines the active time-tilted screening mechanism with the injection of controlled delayed perturbations into the symmetric path to screen the unstable key bits. The measured results demonstrate that the circuit PUF response drops to 1.9 % and 2.9 % BER under temperature fluctuation of −20 °C–80 °C and voltage perturbation of 0.7–1.2V, respectively, and the randomness of the PUF response reaches 99.8 %, the inter-slice Hamming distance reaches 49.57 %, the autocorrelation is only 0.0224, which passes the randomness test of NIST, and the capability of anti-side-channel attack and anti-brutal attack is provided.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.