Integration-The Vlsi Journal最新文献

{"title":"FSMformer: An efficient direction-aware graph transformer for state register detection of gate-level netlist","authors":"Zongtai Li,&nbsp;Liang Yang,&nbsp;Hao Li,&nbsp;Mian Lou,&nbsp;Zeyu Yang,&nbsp;Weidong Xu","doi":"10.1016/j.vlsi.2026.102656","DOIUrl":"10.1016/j.vlsi.2026.102656","url":null,"abstract":"<div><div>Although the use of third-party netlist IP can enhance the quality of integrated circuit products and reduce development cycles, it also introduces potential security vulnerabilities. Identifying state registers in sequential netlists is a commonly adopted technique to assist engineers in understanding the control logic of unknown gate-level netlists. Traditional graph theory-based detection methods, such as RELIC and FSMX-ultra, suffer from low accuracy and high computational complexity. Recent graph neural network-based detection methods, such as ReIGNN, also exhibit limited accuracy, with many data DFFs being misclassified as state DFFs. In this article, we propose a graph transformer-based method, FSMformer, which utilizes bidirectional message passing as the local module and direction-aware linear fast attention as the global module, to enable the simultaneous extraction of structural and functional features from sequential netlists, thereby achieving efficient and accurate detection of state DFFs in large-scale netlists. According to the experimental results, our proposed FSMformer outperforms not only the state-of-the-art graph theory-based method FSMX-ultra and the state-of-the-art GNN-based method ReIGNN, but also various advanced neural network baselines that we employed for state DFFs detection.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102656"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive-precision SIMD architecture for high-throughput and resource-efficient DNN acceleration","authors":"Vasundhara Trivedi ,&nbsp;Harman Singh Bagga ,&nbsp;Gopal Raut ,&nbsp;Santosh Kumar Vishvakarma","doi":"10.1016/j.vlsi.2026.102666","DOIUrl":"10.1016/j.vlsi.2026.102666","url":null,"abstract":"<div><div>Deep Neural Network (DNN) accelerators require high computational throughput and flexible precision support while operating under stringent resource and power constraints. To address these challenges, we propose an adaptive-precision SIMD (Single Instruction, Multiple Data) Processing Element (PE) architecture for signed integer and fixed-point operations that maximizes resource utilization and enhances parallelism in multiply–accumulate (MAC) computations. The design introduces efficient resource reuse during partial product accumulation and supports both symmetric and asymmetric precision modes. Unlike state-of-the-art approaches, the proposed PE dynamically scales computation: processing 16 operands at low precision (4-bit), four operands at medium precision (8-bit), and a single operand at high precision (16-bit). Additionally, it supports asymmetric operations such as 16 <span><math><mo>×</mo></math></span> 4-bit multiplications in parallel, enabling unique flexibility and performance gains. The architecture is implemented and tested on ASIC and FPGA platforms. Accuracy evaluations across different DNN models and datasets show very small losses at reduced precision—less than 1% for LeNet on MNIST, 2.9% for AlexNet on CIFAR-10, 2.2% for VGG16 on CIFAR-10, and 3.5% for VGG16 on ImageNet-1000 compared to float32. Hardware synthesis yields significant improvements, including 46.2% fewer LUTs and 2.45 <span><math><mo>×</mo></math></span> less power on FPGA compared to existing designs. The proposed architecture delivers 2<span><math><mo>×</mo></math></span> higher throughput, upto 4.8<span><math><mo>×</mo></math></span> energy efficiency with 28.57% less area at 65 nm, compared to existing works, making it ideal for applications with variable precision and limited resources.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102666"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low overhead chemical measurement architecture with memristive sensors","authors":"Meenakshi Devi ,&nbsp;Saurabh Khandelwal ,&nbsp;Marek Vidiš ,&nbsp;Tomas Plecenik ,&nbsp;Abusaleh Jabir","doi":"10.1016/j.vlsi.2026.102673","DOIUrl":"10.1016/j.vlsi.2026.102673","url":null,"abstract":"<div><div>Memristors, traditionally considered as non-volatile resistive memories for high-density applications, also exhibit excellent sensitivity to chemicals, making them suitable for chemical sensing with intrinsic memory capabilities. This paper introduces an innovative technique for directly measuring and digitising sensor readings, such as gas concentration, using the switching state of the device, which is influenced by the applied bias voltage or current in the presence of chemicals. When a sensor itself detects and measures a chemical property, its state changes, enabling the direct digitisation of the sensed information. The proposed memristive sensor employs a TiO₂ based memristor as both the sensing and digitising element, and is evaluated using SPICE simulations with hydrogen gas (H₂) at different concentrations. We present a calibration curve that establishes a reliable correlation between pulse counts and chemical concentration, highlighting the consistent relationship between switching behaviour and concentration levels. This method significantly reduces the reliance on separate analogue to digital converters (ADC), simplifying the sensor architecture in terms of power consumption and circuit complexity. Additionally, the inherent nonlinearity of the fabricated devices renders this digitisation method significantly nonlinear, which can provide an added layer of security to the measured information. This approach paves the way for compact, low-power chemical sensing nodes, making them suitable for future integrated environmental monitoring systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102673"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A resource-constrained CNN accelerator for real-time license plate character recognition on FPGA platforms","authors":"George B. Nardes,&nbsp;Thiago H. Rausch,&nbsp;Bruna H. Pereira,&nbsp;Douglas R. Melo,&nbsp;Cesar A. Zeferino","doi":"10.1016/j.vlsi.2026.102654","DOIUrl":"10.1016/j.vlsi.2026.102654","url":null,"abstract":"<div><div>Convolutional Neural Networks (CNNs) are widely used in Automatic License Plate Recognition (ALPR) systems for Optical Character Recognition (OCR). Still, their computational cost often restricts deployment on edge devices. This work presents an 8-bit quantized CNN with a hardware-oriented dataflow designed specifically for OCR of Mercosur and Brazilian license plates. The model was trained using quantization-aware techniques and implemented on two FPGA platforms from different vendors, Altera Cyclone V and AMD Zynq UltraScale+, using the same VHDL architecture. The Zynq UltraScale+ implementation achieves 97.1% OCR accuracy, 2.12 ms latency, and 922 FPS in pipelined mode, while the Cyclone V version delivers 458 FPS with reduced BRAM and DSP usage. Energy measurements show 1.62 mJ per inference on Zynq UltraScale+ and 3.32 mJ on Cyclone V, confirming suitability for low-power, real-time ALPR. The results demonstrate that a portable 8-bit design can maintain accuracy comparable to that of floating-point models while achieving substantial gains in throughput and energy efficiency across heterogeneous FPGA devices.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102654"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EOHEAA: Error-Optimized Hardware-Efficient Approximate Adder for energy-aware error-resilient applications","authors":"Prateek Goyal,&nbsp;Sujit Kumar Sahoo","doi":"10.1016/j.vlsi.2026.102660","DOIUrl":"10.1016/j.vlsi.2026.102660","url":null,"abstract":"<div><div>This work introduces a novel Error-Optimized Hardware-Efficient Approximate Adder (EOHEAA) tailored for error-resilient computing tasks, where precision can be traded for improvements in energy, delay, and resource efficiency. The EOHEAA adopts a strategic method of controlled error propagation, enabling significant enhancement in accuracy metrics such as Mean Error Distance (MED), Mean Relative Error Distance (MRED), and <em>Normalized MED (NMED)</em>, while maintaining minimal hardware overhead. Synthesized on the Artix-7 FPGA <span><math><mrow><mo>(</mo><mi>X</mi><mi>C</mi><mn>7</mn><mi>A</mi><mn>35</mn><mi>T</mi><mo>−</mo><mn>1</mn><mi>C</mi><mi>P</mi><mi>G</mi><mn>236</mn><mi>C</mi><mo>)</mo></mrow></math></span> using Verilog HDL, EOHEAA achieves up to 38.6% reduction in power consumption, an 34% improvement in critical path delay, and notable savings in logic resources compared to conventional and state-of-the-art approximate adder designs. Comprehensive analysis across 8, 16, and 32-bit configurations further confirms its scalability and robustness, with PDP improvements reaching 71.5% in wider designs. Notably, EOHEAA outperforms several existing designs by achieving the lowest RMSE <span><math><mrow><mo>(</mo><mn>32</mn><mo>.</mo><mn>21</mn><mo>)</mo></mrow></math></span>, minimum ED_max <span><math><mrow><mo>(</mo><mn>71</mn><mo>)</mo></mrow></math></span>, and the highest accuracy-to-efficiency balance. ASIC-oriented design flow evaluation is further performed using Cadence Genus with predictive standard-cell libraries to analyze area, power, and timing behavior under advanced technology assumptions. To validate its real-world applicability, EOHEAA has been employed in Edge Detection and Color quantization using K-means clustering, both of which demonstrate high-quality outputs under relaxed accuracy constraints. Furthermore, a lightweight CNN-based validation framework is employed to examine the impact of approximate arithmetic on learning-based workloads, demonstrating that EOHEAA preserves inference accuracy while offering tangible energy and performance benefits. These results collectively position EOHEAA as a strong candidate for next-generation approximate arithmetic units in energy-aware image processing and machine-learning accelerators.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102660"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145928870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Clock tree synthesis in modern VLSI: From foundational algorithms to AI-driven optimization","authors":"Manikandan B ,&nbsp;Karthikumar S","doi":"10.1016/j.vlsi.2026.102665","DOIUrl":"10.1016/j.vlsi.2026.102665","url":null,"abstract":"<div><div>As digital architectures scale to unprecedented complexity, driven by emerging domains such as artificial intelligence, edge inference, and ultra-low-power systems, the strategic orchestration of clock signal delivery has become a cornerstone of integrated circuit design. Clock Tree Synthesis (CTS), a critical stage in the physical design flow, plays a vital role in maintaining synchronous operation, balancing timing constraints, managing dynamic and leakage power, and ensuring signal integrity under aggressive scaling and variable workloads. This review systematically dissects the evolution of CTS, beginning with classical methodologies centered on recursive trees, buffer insertion, and delay balancing, before exploring advanced solutions tailored for variability tolerance, power optimization, and architectural irregularity. In addition, the growing influence of machine learning and data-driven models that replace rigid rule sets with adaptive, layout-aware strategies offers predictive insights and multi-objective optimization throughout the design process. In addition, this study examined specialized use cases in security-conscious designs, aging-resilient circuits, photonic interconnects, and neuromorphic platforms, each demanding unique timing models and synthesis heuristics. This discussion culminates in a reflection on prevailing gaps, including the need for transparent ML integration, benchmark standardization, and holistic frameworks that bridge logical design with physical realization. This work offers a comprehensive perspective on the shifting paradigm of CTS, illuminating its central role in shaping high-performance, energy-efficient, and scalable silicon systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102665"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-power modified basic and feedback-bias common-gate transimpedance amplifiers with a novel bandwidth enhancement technique","authors":"Arash Hosseini,&nbsp;Shahram Mohammadnejad,&nbsp;Mohammad Azim Karami","doi":"10.1016/j.vlsi.2025.102641","DOIUrl":"10.1016/j.vlsi.2025.102641","url":null,"abstract":"<div><div>This article presents two modified low-power basic and feedback-bias common-gate (CG) transimpedance amplifier topologies, which utilize a novel inductor-less current-reuse feedforward technique for 3 dB-bandwidth (BW) extension and relaxing critical trade-offs in CG-based TIAs. The topologies incorporate custom-designed biasing circuits to reduce performance variations across process and temperature. To assess the proposed topologies, mathematical and simulation analyses of both real (with and without zero) and complex conjugate pole conditions, along with noise analysis, have been conducted in modified and conventional structures. The proposed technique creates or adjusts a left-half plane zero through the feedforward path. Then, by neutralizing the dominant pole effect and generating a peaking property, the circuit's bandwidth is enhanced without reducing gain or increasing power consumption. In real pole conditions, the circuit's bandwidth increases by 1.5 <span><math><mrow><mo>∼</mo></mrow></math></span> 2 times, while the input-referred noise is reduced by more than <span><math><mrow><mo>∼</mo></mrow></math></span> 2 times. In the complex conjugate pole state (specifically in feedback-bias CG), the proposed technique reduces the rate of bandwidth reduction caused by the input capacitance (Cin) increase (40 % improvement by changing the Cin from 1.5pF to 2.1 pF). Furthermore, the power consumption decreases by <span><math><mrow><mo>∼</mo></mrow></math></span> 2.4 times compared with the conventional feedback-bias topology. Topologies are validated in various process corners (TT, SS, FF) at different temperatures. In the worst cases, the BW variations of the modified basic and feedback-bias topologies have decreased by 42 % and 16 %, respectively. Additionally, Monte-Carlo and post-layout analysis of the proposed topologies are conducted in 0.18 μm CMOS standard technology.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102641"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Algorithm-hardware co-design of binary neural network for efficient super resolution on FPGA","authors":"Yuanxin Su ,&nbsp;Yihong Wang ,&nbsp;Yushan Pan ,&nbsp;Nan Xiang ,&nbsp;Zhijie Xu ,&nbsp;Jeremy Smith ,&nbsp;Xinfei Guo","doi":"10.1016/j.vlsi.2026.102674","DOIUrl":"10.1016/j.vlsi.2026.102674","url":null,"abstract":"<div><div>The modern Super resolution algorithm have been achieved a great success. However, the high computational complexity and large memory storage of these models hinder their deployment on resource-constrained devices. To address this issue, we propose a novel Binary Neural Network (BNN) architecture specifically designed for Single Image Super Resolution (SISR) tasks. Our approach introduces two key innovations: Dual-Scaling Binary Convolution (DS-BConv) and Dynamic Gradient Attention Binarizing Activation (DGABA). The DS-BConv module employs a dual-phase scaling mechanism to preserve information flow during binarization, while the DGABA function introduces a dynamic gradient attention mechanism that optimizes gradient flow during training. Together, these components enable our BNN to achieve competitive performance on SISR benchmarks while operating within the constraints of binary representations. In addition, we design a highly efficient hardware accelerator architecture for our BNN, leveraging the unique properties of DS-BConv and DGABA to maximize throughput and minimize latency. The accelerator is designed to efficiently handle the computational demands of SISR tasks while maintaining low power consumption, making it suitable for deployment on resource-constrained devices such as mobile phones and embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102674"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ring oscillator-based on-chip aging sensor for recycled IC detection","authors":"S.S. Rekha,&nbsp;K. Sudeendra Kumar","doi":"10.1016/j.vlsi.2026.102677","DOIUrl":"10.1016/j.vlsi.2026.102677","url":null,"abstract":"<div><div>The counterfeit chips are the menace in the semiconductor supply chain, which hurts the revenue and reputation of the original chip makers. The recycled ICs extracted from obsolete electronic equipment form the major part of the counterfeit chips. Recycled counterfeit chips impact the reliability of critical systems, and there is a need to mitigate the recycled chips entering the supply chain. The inclusion of aging sensors in the chips to identify the counterfeit chips is one of the most preferred and well-researched areas. To accurately predict the chip's age is challenging and Ring Oscillator (RO)-based circuits are commonly used in aging sensors. We propose the modified NOR-based Inverter RO aging sensor, which accurately detects recycled chips. The proposed RO-based aging sensor has a relatively low probability of misprediction of an aged chip as a new chip and vice versa, compared to existing RO-based aging sensor techniques. The aging prediction accuracy of the proposed NOR-based inverter RO aging sensor is higher for the chips that have undergone accelerated aging due to high temperatures during their operation. In this work, we integrate the RSA (Rivest Shamir Adleman) cryptographic block presented in the SSTF (Secure Split Test with Functional testing) to make the proposed aging sensor secure against tampering attacks. We validate the proposed aging sensor in Cadence Relxpert using the GPDK 45 nm library and present the simulation and analytical results.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102677"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 180-nm CMOS fully digital chaotic Lorenz system","authors":"Alejandro Silva-Juarez ,&nbsp;Sergio A. Rosales-Nunez ,&nbsp;Luis C. Alvarez-Simon ,&nbsp;Gregorio Zamora-Mejia ,&nbsp;Julio Hernandez-Perez ,&nbsp;Victor H. Carbajal-Gomez ,&nbsp;Jose M. Rocha-Perez ,&nbsp;Alejandro I. Bautista-Castillo","doi":"10.1016/j.vlsi.2026.102667","DOIUrl":"10.1016/j.vlsi.2026.102667","url":null,"abstract":"<div><div>This paper presents the design, Application-Specific Integrated Circuit (ASIC) fabrication, and experimental characterization of a fully digital Lorenz chaotic system in 180 nm CMOS technology. Motivated by the growing demand for high-performance chaotic generators in secure communications, the design originates from a rigorous mathematical formulation, verifying its chaotic behavior via the Kaplan–Yorke dimension estimate. The architecture is based on the forward Euler method, implemented with a 32-bit fixed-point datapath, a control finite-state machine, and integrated 32-to-1 serializers. We detail the complete digital design flow, from RTL to GDSII, using a unified synthesis and place-and-route methodology with the Synopsys Fusion Compiler toolchain. For characterization, the serializers stream the state variables <span><math><mrow><mi>x</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span>, <span><math><mrow><mi>y</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span>, and <span><math><mrow><mi>z</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> to an external FPGA, enabling subsequent transmission to a PC via a UART interface. The integrated circuit was fabricated and tested; experimental measurements successfully validated the chaotic behavior predicted by post-layout simulations. The final design occupies a cell area of 0.873<!--> <!-->mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> and exhibits an estimated static power of 1.02<!--> <!-->mW. Post-layout timing reports indicate that the design meets its target frequencies, achieving a maximum operating frequency above 57<!--> <!-->MHz (with a positive slack of +2.61<!--> <!-->ns on the 50<!--> <!-->MHz clock). The ASIC implementation demonstrates significant advantages in power, density, and speed potential over FPGA-based alternatives, positioning this design as a robust solution for embedded security systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"108 ","pages":"Article 102667"},"PeriodicalIF":2.5,"publicationDate":"2026-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}