Integration-The Vlsi Journal最新文献

{"title":"Dynamical analysis and secure communication application of parameter-controlled multiscroll attractors in memristive chaotic system","authors":"Yijin Liu,&nbsp;Qiang Lai,&nbsp;Huangtao Wang,&nbsp;Yongxian Zhang","doi":"10.1016/j.vlsi.2025.102577","DOIUrl":"10.1016/j.vlsi.2025.102577","url":null,"abstract":"<div><div>The nonlinear constitutive relations and multistable memory characteristics of memristors that render them ideal for chaotic systems, this paper introduces the modular arithmetic operations to the memristor and constructs a parameter controlled multiscroll memristive chaotic system (PCMMCS). The unique nonlinearity of modular arithmetic operations endows the system with distinctive dynamical behaviors. Specifically, PCMMCS exhibits a multiplicity of equilibrium points, the types and locations can be regulated via parametric modulation. This mechanism enables precise control over the number of multiscroll attractors, thereby establishing a direct parametric dependency for attractor configuration. The heterogeneous, homogeneous coexisting attractors and infinite coexisting attractors in the system are formatted via initial value manipulation. A hardware realization of the system has been developed, with multiscroll attractor dynamics successfully observed and characterized on an oscilloscope. The PCMMCS was further developed into a dynamic carrier-differential frequency chaos keying (DC-DFCK) secure communication scheme, and experimental results confirming its operational validity, thereby demonstrating the practical applicability of PCMMCS.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102577"},"PeriodicalIF":2.5,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new circuit configuration for emulating charge/flux controlled memelements","authors":"Shashi Prakash,&nbsp;Mayank Srivastava,&nbsp;Mrutyunjay Rout","doi":"10.1016/j.vlsi.2025.102576","DOIUrl":"10.1016/j.vlsi.2025.102576","url":null,"abstract":"<div><div>The mem-elements are the extension of the memristor idea to memory capacitors and inductors. In this article, an electronic circuit is designed to realize the behavior of all three mem-elements: the memristor, meminductor, and memcapacitor. A key aspect of this study is that the proposed emulator can implement a charge-controlled memristor (CCMR), a flux-controlled memcapacitor (FCMC), and a flux-controlled meminductor (FCMI) using a CCII and Transconductance amplifier (TA), with only a few passive elements and switches. The performance of the proposed emulator is analyzed through simulation results obtained using P-Spice software. The frequency range of the proposed emulator is found to be satisfactory, with an operating frequency of up to 1.2 MHz. Furthermore, these results are validated by available commercial ICs like AD844 and LM13700. The analysis of various parameters, including Monte Carlo simulations, electronic tunability, and non-volatile behavior, demonstrates the strength and robustness of the proposed emulator. Additionally, this emulator has potential applications in neuromorphic computing, as it can mimic associative learning behavior and amoeba-like behavior in memristor and meminductor networks, respectively. The proposed design has also been validated on the breadboard implementation using physical ICs and results are demonstrated.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102576"},"PeriodicalIF":2.5,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamical analysis and FPGA implementation of a memristive non-Hamiltonian conservative hyperchaotic system with extreme multistability","authors":"Runze Lan,&nbsp;Yumeng Wang,&nbsp;Tianxing Xia,&nbsp;Liandong Lin","doi":"10.1016/j.vlsi.2025.102565","DOIUrl":"10.1016/j.vlsi.2025.102565","url":null,"abstract":"<div><div>Recent studies indicate that coupling a memristor with a nonlinear circuit can generate more complex dynamical behaviors. However, research on high-dimensional memristor-based conservative systems remains scarce, and existing low-dimensional memristive systems have yet to exhibit rich dynamic characteristics. In this work, we integrate a magnetically controlled memristor into a conservative chaotic circuit, proposing a novel four-dimensional memristive non-Hamiltonian conservative hyperchaotic system (MHHS) with hidden chaotic dynamics. Through dissipation analysis, Lyapunov exponents, and energy evolution, we verify the system’s non-Hamiltonian conservative properties and hyperchaotic nature. The MHHS system demonstrates high sensitivity to initial conditions and parameters, exhibiting extreme multistability phenomena governed by Hamiltonian energy variations. Phase-space analysis reveals diverse multistable attractors under different initial conditions. Time-series analysis further identifies three distinct transition behaviors: (1) amplitude expansion, (2) quasiperiodic-to-hyperchaotic transitions, and (3) the coexistence of multiple topological states. The system’s chaotic sequences pass the NIST randomness tests, confirming strong pseudorandomness, while Shannon entropy (SE) complexity analysis highlights their high unpredictability. Finally, we implement the MHHS system on FPGA hardware using the fourth-order Runge–Kutta method, experimentally validating its physical realizability. This study not only advances the theoretical understanding of conservative hyperchaotic systems but also provides practical foundations for high-security chaos-based encryption applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102565"},"PeriodicalIF":2.5,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-cost compression architecture based on extended DCT algorithm","authors":"Nedra Jarray ,&nbsp;Majdi Elhajji ,&nbsp;Abdelkrim Zitouni","doi":"10.1016/j.vlsi.2025.102568","DOIUrl":"10.1016/j.vlsi.2025.102568","url":null,"abstract":"<div><div>This paper introduces a low-power, hardware-efficient 2D-DCT architecture aimed at image and video encoding. The architecture implements an optimized Cordic-Loeffler algorithm, which reduces area cost, power consumption, and accelerates the encoding process. The improvement in the Cordic algorithm is achieved by reducing the large number of iteration sequences. Furthermore, the proposed design integrates the Modified Carry Look-Ahead Adder (MCLA) and the Carry Save Adder (CSA) to minimize arithmetic operations and memory requirements. Experimental results demonstrate that the proposed architecture achieves an efficient average peak signal-to-noise ratio (PSNR), especially for endoscopy image compression, along with a reduction in addition/shift operations compared to other competitive Cordic-DCT algorithms.</div><div>The proposed architecture was implemented using Xilinx ISE 13.1 for the Virtex5-FPGA, with an operating frequency of 254.6 MHz and a power consumption of 39 mW at 100 MHz. These results surpass the performance of most previous architectures for Virtex-4/Virtex-5 FPGA implementations. According to performance estimations for ASIC implementation using TSMC 130 nm technology, the proposed design dissipates approximately 4.68 mW at 100 MHz, which is notably lower than that of previous works. Thus, the proposed 2D-DCT architecture is particularly suitable for low-power, high-quality codecs, making it ideal for battery-powered embedded systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102568"},"PeriodicalIF":2.5,"publicationDate":"2025-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cross-regulation characteristics of non-ideal single-inductor dual-output buck converter with voltage controlled","authors":"Bingli Liu ,&nbsp;Jiarong Wu ,&nbsp;Liping Luo ,&nbsp;Chunming Wen ,&nbsp;Weilin Wu ,&nbsp;Hailong Ma","doi":"10.1016/j.vlsi.2025.102575","DOIUrl":"10.1016/j.vlsi.2025.102575","url":null,"abstract":"<div><div>Single-inductor multiple-output (SIMO) dc-dc converters are widely adopted in smart homes due to their high efficiency and small circuit volume. However, cross-regulation (CR) seriously influences the dynamic performance and the stability of SIMO dc-dc converters. In this paper, the CR characteristics of a non-ideal single-inductor dual-output (NI-SIDO) Buck converter with voltage control are analyzed, which includes parasitic resistors of the inductor and output capacitors. A nonlinear mathematical model and small-signal circuit are built, deducing the CR transfer functions and CR impedances. Therefore, the important factors affecting the CR are explored. Moreover, the CR characteristics are studied by the Bode plot under the common-mode voltage and differential-mode voltage control. The simulation results demonstrate that increasing the parasitic resistor of the inductor reduces the CR between the output branches. Furthermore, when the parasitic resistor of a branch output capacitor increases, the CR of the other output branch decreases accordingly. Finally, an experimental prototype is constructed to provide the correctness of the theoretical analysis.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102575"},"PeriodicalIF":2.5,"publicationDate":"2025-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low power current-mode hybrid computing architecture signal processing circuit","authors":"Yuhang Lu,&nbsp;Huimin Liu","doi":"10.1016/j.vlsi.2025.102571","DOIUrl":"10.1016/j.vlsi.2025.102571","url":null,"abstract":"<div><div>To address the increasingly prominent physical limitations and energy efficiency challenges in digital circuits, this paper proposes an innovative current-mode computing paradigm and presents a low-power current-mode hybrid computing architecture specifically designed for signal processing circuits. The core current-mode circuits of the architecture employ the MOSFET Translinear loop (MTL) principle. The key contributions include the structural simplification of the MTL nonlinear computing unit, flipped voltage follower biasing, which enables reliable low-voltage operation, and a significant reduction in silicon area and power consumption. The proposed design demonstrates versatile capabilities for implementing nonlinear functions, including square, absolute value, square root, and multiplication operations. By incorporating multiplier circuits, the design achieves a configurable-coefficient hybrid current-mode low-voltage discrete third-order Finite Impulse Response (FIR) filter, effectively mitigating the high-power consumption and area overhead caused by high-bit-width operations and fractional coefficients in conventional digital filter implementations. Additionally, a 6-bit flash current-mode ADC is introduced to serve as an interface between current-domain analog circuits and digital systems. Simulation results based on 28 nm CMOS technology with a 0.9V supply voltage confirm the functional robustness of the proposed circuit across temperature variations and process corners. Compared with conventional MTL implementations, the proposed solution not only achieves enhanced stability under low-voltage operation but also preserves computational accuracy comparable to 32-bit floating-point digital filters. Most notably, the hybrid architecture demonstrates significant improvements in both power efficiency (63 % reduction) and silicon area utilization (25 % reduction), setting a new state-of-the-art standard for energy-efficient signal processing systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102571"},"PeriodicalIF":2.5,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology","authors":"Anish Paul ,&nbsp;Siya Sharma ,&nbsp;Kulbhushan Sharma","doi":"10.1016/j.vlsi.2025.102574","DOIUrl":"10.1016/j.vlsi.2025.102574","url":null,"abstract":"<div><div>As SRAM cells are scaled down to advanced technology nodes, their sensitivity to radiation-induced soft errors increases significantly, making them less reliable for use in critical environments like aerospace and defense. To address this issue, a new 13-transistor radiation-hardened SRAM cell, called SEFCR-13T, is proposed using 18 nm FinFET technology. The cell uses a feedback-cutting technique and redundant node structure to improve soft-error tolerance while maintaining a balance among power, speed, and area. The SEFCR-13T cell is designed and simulated using Cadence Virtuoso and compared with five existing SRAM cells: Conventional 6T, Hybrid 12T, TRD 9T, RHIRS 12T, and RRS 14T. Key performance parameters such as critical charge, static noise margins (SNM), power consumption, delay, and area were evaluated across a voltage range of 0.6 V–1.0 V. At 0.7 V, the proposed SEFCR 13T shows the highest critical charge of 3.67 fC, which is 2.65 × higher than the 6T SRAM and 1.2 × higher than RHIRS 12T. It also achieves a write SNM improvement of up to 2.95 × and read SNM improvement of 2.67 × compared to the 6T cell. Read and write delays are reduced by 2.5 × and 1.8 × , respectively, while read power is reduced by 2.4 × . The proposed design also achieves the highest overall figure of merit (FOM), 17 × better than 6T SRAM. These results show that the proposed cell provides excellent improvement in soft-error resistance and overall stability, making it a strong candidate for reliable memory design in radiation-prone and low-power applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102574"},"PeriodicalIF":2.5,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Gated-SRAM and novel header–footer multiplexer based ultra low power Look-Up Table design","authors":"Meeniga Srikanth Reddy ,&nbsp;Debanjali Nath ,&nbsp;Debajit Deb","doi":"10.1016/j.vlsi.2025.102566","DOIUrl":"10.1016/j.vlsi.2025.102566","url":null,"abstract":"<div><div>In this paper we propose a two-level power gating technique which could incorporate significant leakage power reduction in pass transistor (PTL) and transmission gate (T-Gate) based look up table (LUT), designed using 45 nm generic library from cadence. First level power gating at SRAM array resulted in reduced subthreshold and gate leakage across the devices. A novel Header/Footer logic has been implemented to power-gate MUX logic of LUT. Unlike conventional header/footer schemes that only cut off the supply or ground to reduce leakage, our diode-connected header and feedback-controlled footer enable parallel output level restoration while simultaneously suppressing leakage. The feedback-controlled footer (NFD) ensures that weak logic levels from the multiplexer do not propagate to the output buffer, thereby reducing subthreshold and gate leakage. The Power-gated SRAM average power dissipation has been observed to reduce from 6.09 pW to 1.884 pW (write-1 operation). Power gating in the SRAM array resulted in a three order magnitude reduction in average power from 17.01<span><math><mi>μ</mi></math></span> W to 153.05 nW at pass transistor-based LUT level. Similar average power reduction up to 3-orders have also been observed for T-Gate based MUX-LUT with power gated SRAMs from 16.42<span><math><mi>μ</mi></math></span> W to 688.3 nW. The values were further reduced by more than three orders for both PTL and T-Gate based designs when novel header/footer logic was applied at the MUX level. Post-layout simulations further validate that parasitic effects reduce overall power dissipation compared to the pre-layout results for conventional and gated SRAM based LUTs. Additionally, the CLB implementation demonstrates ultra-low power of 389.8 pW in low-performance mode (HP=0), highlighting the practical advantage of the proposed architecture over conventional LUT-based designs. The implementation of proposed design impose no observable delay of data transfer between input of SRAM to final output of CLB.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102566"},"PeriodicalIF":2.5,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145221216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leveraging asynchronous quantum secretary bird Generative propagation adversarial attention networks for FIR filter design in ECG applications","authors":"Theivanathan G,&nbsp;Murukesh C","doi":"10.1016/j.vlsi.2025.102569","DOIUrl":"10.1016/j.vlsi.2025.102569","url":null,"abstract":"<div><div>The escalating demand for better ECG signal analysis has created a demand for designs of better filters. This paper provides an alternate methodology towards proposing filter designs, through the use of Asynchronous Quantum Secretary Bird Generative Propagation Adversarial Attention Networks (Asyn-Qan-SBG-P2AN). In this proposal, the optimal filter coefficients are derived through the employment of Quantum Generative Adversarial Networks (QGAN), filter response characteristics are derived using Asynchronous Propagation Attention Networks (APAN) for adaptive signal feature extraction, and finally, using the Secretary Bird Optimization Algorithm (SBOA) based upon a filter's role, couples with Asyn-Qan-SBG-P2AN in differentiating ECG signals from other physiological measurements. Technology and method have combined to offer a generation of smart, adaptive and learning-based filter design in ECG applications. Our band-pass FIR filter has marked improvements in signal clarity, noise suppression, and resources being used to offer newly stunned opportunities for signal processing using lower specifications. Contributor offers a power consumption of 12 mW, Area 10 mm², Operating speed 300 MHz, and Frequency 4.8 GHz. The parameters also provide evidence that machine learning solutions can be used in real-time processing of ECG signals while capturing diagnostic AUCs, and provide a coronation for lower power possible in wearables.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102569"},"PeriodicalIF":2.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145221217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An analytical approach and fine-tuning strategy for PCB placement optimization","authors":"Hongyu Zhao,&nbsp;Yunhao Hu,&nbsp;Zhuomin Chai,&nbsp;Peng Wei,&nbsp;Shupei He,&nbsp;Wei Liu","doi":"10.1016/j.vlsi.2025.102567","DOIUrl":"10.1016/j.vlsi.2025.102567","url":null,"abstract":"<div><div>As the foundation for connecting and supporting various electronic components, Printed Circuit Boards (PCBs) play an important role in modern electronic systems. The quality of PCBs physical design directly impacts the performance, reliability, and cost of the entire circuit. However, the automation of PCB physical design remains an issue that has not been fully resolved. In order to obtain high quality PCBs, component placement is the most important stage in an PCB design, and its result significantly influences both the wirelength and the overall routability of the design. Hence, we propose an analytical automated placement algorithm tailored for PCBs in this paper, including three stages: global placement, legalization, and fine-tuning. We perform an extensive study with 10 PCB designs and an open-source router. We show that the quality of our placement results is closer to that of manual. Compared to traditional algorithms, our analytical approach achieves higher routing completion rates and significantly reduces placement runtime.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102567"},"PeriodicalIF":2.5,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145221215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}