Fei Yu , Xuqi Wang , Rongyao Guo , Zhijie Ying , Shuo Cai , Jie Jin
{"title":"Dynamical analysis, hardware implementation, and image encryption application of new 4D discrete hyperchaotic maps based on parallel and cascade memristors","authors":"Fei Yu , Xuqi Wang , Rongyao Guo , Zhijie Ying , Shuo Cai , Jie Jin","doi":"10.1016/j.vlsi.2025.102475","DOIUrl":"10.1016/j.vlsi.2025.102475","url":null,"abstract":"<div><div>In this paper, the construction of a series of 4D discrete hyperchaotic maps is achieved through employing parallel and cascade operations on discrete memristors (DMs). Initially, DMs are integrated in both parallel and cascade configurations to form parallel DMs and cascade DMs, respectively. Subsequently, the nonlinear terms derived from these parallel and cascade DMs are coupled into the sine map and logistic map, generating four 4D discrete hyperchaotic maps that exhibit diverse dynamical behaviors. The dynamical properties of the proposed maps are systematically investigated through the analysis of dynamical behaviors and the distribution of the first Lyapunov exponent (LE). The dynamical phenomena of the hyperchaotic maps are further elucidated by examining the initial-value-dependent LE spectrum, bifurcation diagrams, and the mean values of state variables. Notably, the observed dynamical phenomena encompass four types of rare hyperchaotic behaviors, discharge pattern transitions, and coexistence phenomena. Moreover, the spectral entropy complexity is calculated across various parameter planes, revealing a high degree of complexity in the proposed system. The hyperchaotic map is implemented on Field-Programmable Gate Array (FPGA) hardware implementation platform, demonstrating its practical feasibility. Furthermore, an efficient image encryption scheme is designed, and its robust security performance is validated through comprehensive security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102475"},"PeriodicalIF":2.2,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-performance radiation hardened latch using Schmitt trigger","authors":"Niraj Kumar , Chaudhary Indra Kumar , Neeta Pandey","doi":"10.1016/j.vlsi.2025.102478","DOIUrl":"10.1016/j.vlsi.2025.102478","url":null,"abstract":"<div><div>This paper presents a novel 45 nm CMOS radiation-hardened latch design for low-voltage applications. This paper focusses on the Schmitt trigger-based latch, which enhances robustness through increased node capacitance, providing better noise tolerance. While other types of latch designs uses redundant nodes for radiation hardening but faces reliability issues in modern technologies. This work presents two transient fault-tolerant latch designs based on a seven-transistor Schmitt trigger (STST). The proposed latch circuits are designed and implemented under the 45 nm CMOS technology node. The proposed latch provides the single event upset (SEU) tolerance using the STST latch to hold the correct state. The proposed designs for making STST latch radiation hardened is to increase the node capacitance at susceptible nodes by adding an STST block. The first design STST latch has a lower delay of 57%, a higher critical charge of 28.03%, a lower power of 43.86%, a lower power delay product (PDP) of 75.86%, and a higher critical charge to power delay area product ratio (QPAR) of 494.12% with a decreased area of 12.87% than recently proposed latches. The second design, the cascode seven-transistor Schmitt trigger (CSTST) latch, has a cascode feedback loop in place of a transmission gate and inverter with an improved critical charge of 11.74% and a higher critical charge to power delay area product ratio (QPAR) of 11.73% than the STST latch without an area increase.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102478"},"PeriodicalIF":2.2,"publicationDate":"2025-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144613824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An 8T SRAM cell for high-speed sub-threshold operation with dynamic body biasing","authors":"Anshumat Dinesh , Yogita Chopra , Poornima Mittal","doi":"10.1016/j.vlsi.2025.102480","DOIUrl":"10.1016/j.vlsi.2025.102480","url":null,"abstract":"<div><div>This paper presents a Transmission Gate based 8T SRAM cell with dynamic body biasing, featuring a SNM-free read port. The memory core uses 5 transistors (4 for cross-coupled inverters and 1 for feedback control). The design demonstrates consistent Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) across 27<sup><em>°</em></sup>C-75<sup><em>°</em></sup>C, while the write margin (WM) increases linearly with temperature up to 75<sup><em>°</em></sup>C before a slight decline. N-curve metrics—SVNM, SINM, WTV, and WTI—reveal stability trends: SVNM/SINM mirror HSNM/RSNM, WTV improves with temperature, and WTI degrades. Current parameters scale exponentially with supply voltage, whereas WTV and WM show linear voltage dependence. Power consumption remains stable across the tested temperature range but rises sharply with supply voltage. Write delay reduces significantly at higher voltages. The cell employs Dynamic Threshold MOS (DTMOS) logic, enhancing write speed (52 % faster than comparable designs) with an average write delay of 14.9 ns (7.35 ns for ‘0’). This speed improvement incurs higher power due to DTMOS-driven currents, with the write power being 4.3 times higher than the average of the other cells. The read power, however, is exactly equal to the average value of the other cells being at 1.47 nW, and static power is slightly higher than the average power of the other cells. The design provides stability in line with other cells tested, exceeding the immunity to current noise during read operations. The compact layout occupies 1.68 <span><math><mrow><mi>μ</mi><msup><mi>m</mi><mn>2</mn></msup></mrow></math></span>, smaller than several counterparts. The Design is optimized for speed while having stability and layout area in accordance with the average of the other cells, the power consumption of the cell is the attribute in which the design shows a strikingly inferior performance when compared to other cells.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102480"},"PeriodicalIF":2.2,"publicationDate":"2025-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144634480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cascode subthreshold PTAT source bandgap voltage reference circuit","authors":"Komal Duhan, Neelam Rup Prakash, Jasbir Kaur, Sameeksha Munjal","doi":"10.1016/j.vlsi.2025.102483","DOIUrl":"10.1016/j.vlsi.2025.102483","url":null,"abstract":"<div><div>Bandgap Voltage reference (BGR) are crucial components in analog circuits. This paper introduces a BGR circuit designed in the subthreshold region using Cadence Generic Process Design Kits (GPDK) 90 nm technology. The cascoding technique is used to remove channel length modulation effect to get stable output voltage for a wider range of temperature and supply voltage. The proposed circuit produces a reference voltage of 344 mV, consuming 94.64 nW power at room temperature with a supply voltage starting from 550 mV. The temperature coefficient is measured to be 8.337 ppm/<sup>O</sup>C within a temperature range of −45 <sup>O</sup>C to 170 <sup>O</sup>C with a line regulation of 0.017 %/V. The designed BGR circuit can be used in analog applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102483"},"PeriodicalIF":2.2,"publicationDate":"2025-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144631660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Soft fault diagnosis in analog electronic circuits using supervised machine learning","authors":"M.I. Dieste-Velasco","doi":"10.1016/j.vlsi.2025.102482","DOIUrl":"10.1016/j.vlsi.2025.102482","url":null,"abstract":"<div><div>Analog circuits are commonly used in a wide range of industrial applications, and their assessment is of great importance to ensure proper functionality and prevent faults. However, this task is not as fully developed and is significantly less advanced compared to the assessment of digital circuits, as soft faults are particularly difficult to detect in analog circuits. This study addresses the application of supervised classification techniques for the detection and classification of soft faults in analog circuits. A feature extraction methodology is proposed based on voltage measurements at key circuit points and across different frequencies, enabling precise characterization of system behavior. From this feature, a benchmark employing different machine learning methods was used. The evaluated classifiers include k-Nearest Neighbors (KNN), Naïve Bayes (NB), Discriminant Analysis Classifier (DAC), Classification Decision Tree (CDT), Random Forest (RF), Support Vector Machines (SVM) and Artificial Neural Networks (ANN). Each model was optimized through hyperparameter tuning and validated using cross-validation techniques. The results indicate that ANN and SVM achieved the best performance, attaining an accuracy of 97.92 % and 97.22 % on test data, with a global Matthews Correlation Coefficient (MCC) of 97.76 % and 97.01 %, respectively. Although RF obtained the highest training accuracy (99.39 %), its performance significantly dropped during testing (93.06 %, MCC of 92.52 %), indicating overfitting. Additionally, models such as KNN and DAC demonstrated solid performance, whereas NB and CDT were the least effective. These findings highlight the importance of carefully selecting both the feature set and the classification model for fault detection in electronic circuits. A Sallen-Key band-pass filter was used as the circuit under test (CUT), as soft fault classification in this type of circuit is particularly challenging. This study demonstrates that it is possible to accurately predict faults in circuits similar to the one analyzed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102482"},"PeriodicalIF":2.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kaijie Li , Liang Pang , Xudong Zhang , Yutao Miao , Yushi Zhang
{"title":"Efficient high dimensional yield analysis for SRAM circuits via stack model and adaptive sampling","authors":"Kaijie Li , Liang Pang , Xudong Zhang , Yutao Miao , Yushi Zhang","doi":"10.1016/j.vlsi.2025.102477","DOIUrl":"10.1016/j.vlsi.2025.102477","url":null,"abstract":"<div><div>Statistical yield analysis provides the relationship between performance and reliability in SRAM design at the expense of large simulation cost. In this paper, we developed a stack model based yield analysis method to minimize the simulation cost. In our stack model, a linear prior function is first modeled with sparse constraint to fit the overall trend and achieve feature selection. In order to ensure the accuracy near failure region, the modeling center will be shifted to the failure boundary by random-walk sampling. And the other two classical ensemble models will be constructed with the adaptive resampling strategy. Finally, a Machine Learning (ML) model is applied to best combine the predictions derived from these base models. When trained with small datasets generated from 28 nm memory circuits, our stack model shows competitive accuracy and efficiency compared with other state-of-art models.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102477"},"PeriodicalIF":2.2,"publicationDate":"2025-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Richard Ravasz, Viera Stopjakova, David Maljar, Daniel Arbet, Lukas Nagy, Martin Kovac
{"title":"Development of slope detection ASIC for on-chip current sensing in voltage converters","authors":"Richard Ravasz, Viera Stopjakova, David Maljar, Daniel Arbet, Lukas Nagy, Martin Kovac","doi":"10.1016/j.vlsi.2025.102471","DOIUrl":"10.1016/j.vlsi.2025.102471","url":null,"abstract":"<div><div>This research centers on the design and analysis of an on-chip indirect approach aimed at estimating the output load current in a DC–DC flyback converter. This indirect method for estimating electric current relies on assessing the slope of the output voltage from the converter on the external filter capacitor during discharge phases. Consequently, this slope data can be effectively harnessed to control the converter’s switches. The proposed circuit operates on a power supply of 1.2 V and was designed using standard 65 nm CMOS technology. The designed slope detector circuit has the capability of measuring current within the range of one to hundreds of milliamperes. Given its predominantly digital nature, the circuit provides inherent robustness against variations in process, temperature, and supply voltage.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102471"},"PeriodicalIF":2.2,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhaoxiong Guan, Mingxin Liu, Jinqiang Xu, Cong Lin
{"title":"A hybrid entropy source scheme for true random number generator","authors":"Zhaoxiong Guan, Mingxin Liu, Jinqiang Xu, Cong Lin","doi":"10.1016/j.vlsi.2025.102473","DOIUrl":"10.1016/j.vlsi.2025.102473","url":null,"abstract":"<div><div>True random number generators (TRNGs) are gaining increasing attention as essential components in information security systems. In this paper, a dual-path reconfigurable ring (DPRR) that generates both jitter and metastability is proposed. Its fundamental unit consists of seven XOR gates and two 2-to-1 multiplexers (MUXs). The advantage of this method lies in utilizing the ability of XOR gates to quickly accumulate jitter and the characteristic of the 2-to-1 MUX to switch the loop path, simultaneously inducing jitter and instability in the proposed scheme. The DPRR-based TRNG was deployed on the Field Programmable Gate Array (FPGA) platforms with Artix-7 and Kintex-7 using automatic layout and routing mode, which consumed 33 Look-up Tables (LUTs) and 12 D Flip-Flops (DFFs) to achieve 200/300 Mbps throughput. Experimental results demonstrate that the random sequences generated by this TRNG pass the NIST SP800-22, NIST SP800-90B, AIS-31, and robustness test without requiring post-processing circuits.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102473"},"PeriodicalIF":2.2,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144580924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search","authors":"Ying Wu, Zheyu Yan, Xunzhao Yin, Lenian He, Cheng Zhuo","doi":"10.1016/j.vlsi.2025.102469","DOIUrl":"10.1016/j.vlsi.2025.102469","url":null,"abstract":"<div><div>Deep Neural Networks (DNNs) are prevalent solutions for perception tasks, with energy efficiency being particularly critical for deployment on edge platforms. Various studies have proposed efficient DNN edge deployment solutions; however, an important aspect – approximate computing – has been overlooked. Current research primarily focuses on designing approximate circuits for specific DNN models, neglecting the influence of DNN architecture design. To address this gap, this paper proposes a software–hardware co-exploration framework for approximate DNN accelerator design that jointly explores approximate multipliers and neural architectures. This framework, termed Approximate Neural Architecture Search (ANAS), tackles two main challenges: (1) efficiently evaluating the impact of approximate multipliers on application performance and accelerator design for each sample, and (2) effectively navigating a large design space to identify optimal configurations. The framework employs a recurrent neural network-based reinforcement learning algorithm to identify an optimal approximate multiplier-DNN architecture pair that balances DNN accuracy and hardware cost. Experimental results demonstrate that ANAS achieves comparable accuracy while reducing energy consumption and latency by up to 40% compared to state-of-the-art NAS-based methods.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102469"},"PeriodicalIF":2.2,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144556815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wesley Grignani , Felipe Viel , Douglas A. Santos , Luigi Dilillo , Douglas R. Melo
{"title":"A fault-tolerant CCSDS 123 hardware accelerator for space applications","authors":"Wesley Grignani , Felipe Viel , Douglas A. Santos , Luigi Dilillo , Douglas R. Melo","doi":"10.1016/j.vlsi.2025.102465","DOIUrl":"10.1016/j.vlsi.2025.102465","url":null,"abstract":"<div><div>Remote sensing techniques in space applications utilize HSIs (Hyperspectral Images) to gather vast amounts of Earth data. The high data volumes associated with HSIs pose significant challenges for storage and processing capabilities in space systems, emphasizing the need for efficient compression. Given the susceptibility of space-based systems to faults due to harsh environmental conditions, fault tolerance mechanisms are essential for ensuring reliable operation. This work presents a low-cost and fault-tolerant CCSDS 123 HSI compressor that employs TMR (Triple Modular Redundancy) and Hamming ECC (Error Correcting Code) to mitigate SEUs (Single Event Upsets). We present the compressor in a standard version, followed by partially protected and fully protected versions, each incorporating varying hardening levels in different circuit components. We performed a fault injection campaign to assess the reliability of all implementations. Results show that the standard version exhibited a high error rate of 97.9%, which presented a significant reduction in the partially hardened versions, reaching no error propagation in the fully hardened version. The standard solution presented the lowest resource utilization and can process 20.57 MSa/s, considering the Hyperion image configuration. Furthermore, all implementations accelerated the application, resulting in a performance improvement of up to 24<span><math><mo>×</mo></math></span> compared to a software solution.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102465"},"PeriodicalIF":2.2,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144548682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}