Integration-The Vlsi Journal最新文献

Dynamical analysis, hardware implementation, and image encryption application of new 4D discrete hyperchaotic maps based on parallel and cascade memristors 基于并联和级联记忆电阻器的新型4D离散超混沌映射的动态分析、硬件实现和图像加密应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-19 DOI: 10.1016/j.vlsi.2025.102475

Fei Yu , Xuqi Wang , Rongyao Guo , Zhijie Ying , Shuo Cai , Jie Jin

{"title":"Dynamical analysis, hardware implementation, and image encryption application of new 4D discrete hyperchaotic maps based on parallel and cascade memristors","authors":"Fei Yu , Xuqi Wang , Rongyao Guo , Zhijie Ying , Shuo Cai , Jie Jin","doi":"10.1016/j.vlsi.2025.102475","DOIUrl":"10.1016/j.vlsi.2025.102475","url":null,"abstract":"<div><div>In this paper, the construction of a series of 4D discrete hyperchaotic maps is achieved through employing parallel and cascade operations on discrete memristors (DMs). Initially, DMs are integrated in both parallel and cascade configurations to form parallel DMs and cascade DMs, respectively. Subsequently, the nonlinear terms derived from these parallel and cascade DMs are coupled into the sine map and logistic map, generating four 4D discrete hyperchaotic maps that exhibit diverse dynamical behaviors. The dynamical properties of the proposed maps are systematically investigated through the analysis of dynamical behaviors and the distribution of the first Lyapunov exponent (LE). The dynamical phenomena of the hyperchaotic maps are further elucidated by examining the initial-value-dependent LE spectrum, bifurcation diagrams, and the mean values of state variables. Notably, the observed dynamical phenomena encompass four types of rare hyperchaotic behaviors, discharge pattern transitions, and coexistence phenomena. Moreover, the spectral entropy complexity is calculated across various parameter planes, revealing a high degree of complexity in the proposed system. The hyperchaotic map is implemented on Field-Programmable Gate Array (FPGA) hardware implementation platform, demonstrating its practical feasibility. Furthermore, an efficient image encryption scheme is designed, and its robust security performance is validated through comprehensive security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102475"},"PeriodicalIF":2.2,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications 用于生物医学应用的低成本区域效率改良俄罗斯农民倍增器（MRPM）

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-19 DOI: 10.1016/j.vlsi.2025.102474

Guru Siva Subramanian V., Deepika Sree T.N. , Aditya S.

{"title":"A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications","authors":"Guru Siva Subramanian V., Deepika Sree T.N. , Aditya S.","doi":"10.1016/j.vlsi.2025.102474","DOIUrl":"10.1016/j.vlsi.2025.102474","url":null,"abstract":"<div><div>The essentiality of efficient hardware multipliers has increased as they have a huge impact on the performance and the power consumption of digital systems. This work proposes a novel 8-bit unsigned multiplier architecture which combines the Modified Russian Peasant algorithm with a Kogge-Stone adder. The aim of the proposed design is to minimize resource usage and power consumption while retaining high speed and accuracy. The effective optimization of the multiplier design led to a significant reduction in area utilization and overall power consumption, making it highly suitable for implementing in resource constrained systems. The design is validated using Xilinx Vivado tool and is implemented on Nexys A7 FPGA board. The results show that the proposed multiplier utilizes fewer devices (50%–70% less) and has comparative speed and power consumption with respect to the conventional multipliers. The proposed multiplier design can be used for biomedical systems such as wearable health monitors and implantable medical devices, where compact size and energy efficiency are key considerations. This efficient multiplier architecture ensures prolonged battery life and reliable performance, enabling advanced signal processing tasks such as signal filtering, enhancement of medical imaging and noise reduction in hearing aids. These features emphasize the multiplier’s potential to enable substantial enhancements in high-performance, area-sensitive, and power-sensitive biomedical applications, which will contribute to the forthcoming compact and energy-efficient healthcare systems.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102474"},"PeriodicalIF":2.2,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance radiation hardened latch using Schmitt trigger 高性能辐射硬化闩锁使用施密特触发器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-13 DOI: 10.1016/j.vlsi.2025.102478

Niraj Kumar , Chaudhary Indra Kumar , Neeta Pandey

{"title":"High-performance radiation hardened latch using Schmitt trigger","authors":"Niraj Kumar , Chaudhary Indra Kumar , Neeta Pandey","doi":"10.1016/j.vlsi.2025.102478","DOIUrl":"10.1016/j.vlsi.2025.102478","url":null,"abstract":"<div><div>This paper presents a novel 45 nm CMOS radiation-hardened latch design for low-voltage applications. This paper focusses on the Schmitt trigger-based latch, which enhances robustness through increased node capacitance, providing better noise tolerance. While other types of latch designs uses redundant nodes for radiation hardening but faces reliability issues in modern technologies. This work presents two transient fault-tolerant latch designs based on a seven-transistor Schmitt trigger (STST). The proposed latch circuits are designed and implemented under the 45 nm CMOS technology node. The proposed latch provides the single event upset (SEU) tolerance using the STST latch to hold the correct state. The proposed designs for making STST latch radiation hardened is to increase the node capacitance at susceptible nodes by adding an STST block. The first design STST latch has a lower delay of 57%, a higher critical charge of 28.03%, a lower power of 43.86%, a lower power delay product (PDP) of 75.86%, and a higher critical charge to power delay area product ratio (QPAR) of 494.12% with a decreased area of 12.87% than recently proposed latches. The second design, the cascode seven-transistor Schmitt trigger (CSTST) latch, has a cascode feedback loop in place of a transmission gate and inverter with an improved critical charge of 11.74% and a higher critical charge to power delay area product ratio (QPAR) of 11.73% than the STST latch without an area increase.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102478"},"PeriodicalIF":2.2,"publicationDate":"2025-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144613824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 8T SRAM cell for high-speed sub-threshold operation with dynamic body biasing 一种8T SRAM单元，用于具有动态体偏置的高速亚阈值操作

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-13 DOI: 10.1016/j.vlsi.2025.102480

Anshumat Dinesh , Yogita Chopra , Poornima Mittal

{"title":"An 8T SRAM cell for high-speed sub-threshold operation with dynamic body biasing","authors":"Anshumat Dinesh , Yogita Chopra , Poornima Mittal","doi":"10.1016/j.vlsi.2025.102480","DOIUrl":"10.1016/j.vlsi.2025.102480","url":null,"abstract":"<div><div>This paper presents a Transmission Gate based 8T SRAM cell with dynamic body biasing, featuring a SNM-free read port. The memory core uses 5 transistors (4 for cross-coupled inverters and 1 for feedback control). The design demonstrates consistent Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) across 27<sup><em>°</em></sup>C-75<sup><em>°</em></sup>C, while the write margin (WM) increases linearly with temperature up to 75<sup><em>°</em></sup>C before a slight decline. N-curve metrics—SVNM, SINM, WTV, and WTI—reveal stability trends: SVNM/SINM mirror HSNM/RSNM, WTV improves with temperature, and WTI degrades. Current parameters scale exponentially with supply voltage, whereas WTV and WM show linear voltage dependence. Power consumption remains stable across the tested temperature range but rises sharply with supply voltage. Write delay reduces significantly at higher voltages. The cell employs Dynamic Threshold MOS (DTMOS) logic, enhancing write speed (52 % faster than comparable designs) with an average write delay of 14.9 ns (7.35 ns for ‘0’). This speed improvement incurs higher power due to DTMOS-driven currents, with the write power being 4.3 times higher than the average of the other cells. The read power, however, is exactly equal to the average value of the other cells being at 1.47 nW, and static power is slightly higher than the average power of the other cells. The design provides stability in line with other cells tested, exceeding the immunity to current noise during read operations. The compact layout occupies 1.68 <span><math><mrow><mi>μ</mi><msup><mi>m</mi><mn>2</mn></msup></mrow></math></span>, smaller than several counterparts. The Design is optimized for speed while having stability and layout area in accordance with the average of the other cells, the power consumption of the cell is the attribute in which the design shows a strikingly inferior performance when compared to other cells.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102480"},"PeriodicalIF":2.2,"publicationDate":"2025-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144634480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cascode subthreshold PTAT source bandgap voltage reference circuit 级联码亚阈值PTAT源带隙电压参考电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-13 DOI: 10.1016/j.vlsi.2025.102483

Komal Duhan, Neelam Rup Prakash, Jasbir Kaur, Sameeksha Munjal

引用次数: 0

Soft fault diagnosis in analog electronic circuits using supervised machine learning 基于监督机器学习的模拟电路软故障诊断

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-11 DOI: 10.1016/j.vlsi.2025.102482

M.I. Dieste-Velasco

{"title":"Soft fault diagnosis in analog electronic circuits using supervised machine learning","authors":"M.I. Dieste-Velasco","doi":"10.1016/j.vlsi.2025.102482","DOIUrl":"10.1016/j.vlsi.2025.102482","url":null,"abstract":"<div><div>Analog circuits are commonly used in a wide range of industrial applications, and their assessment is of great importance to ensure proper functionality and prevent faults. However, this task is not as fully developed and is significantly less advanced compared to the assessment of digital circuits, as soft faults are particularly difficult to detect in analog circuits. This study addresses the application of supervised classification techniques for the detection and classification of soft faults in analog circuits. A feature extraction methodology is proposed based on voltage measurements at key circuit points and across different frequencies, enabling precise characterization of system behavior. From this feature, a benchmark employing different machine learning methods was used. The evaluated classifiers include k-Nearest Neighbors (KNN), Naïve Bayes (NB), Discriminant Analysis Classifier (DAC), Classification Decision Tree (CDT), Random Forest (RF), Support Vector Machines (SVM) and Artificial Neural Networks (ANN). Each model was optimized through hyperparameter tuning and validated using cross-validation techniques. The results indicate that ANN and SVM achieved the best performance, attaining an accuracy of 97.92 % and 97.22 % on test data, with a global Matthews Correlation Coefficient (MCC) of 97.76 % and 97.01 %, respectively. Although RF obtained the highest training accuracy (99.39 %), its performance significantly dropped during testing (93.06 %, MCC of 92.52 %), indicating overfitting. Additionally, models such as KNN and DAC demonstrated solid performance, whereas NB and CDT were the least effective. These findings highlight the importance of carefully selecting both the feature set and the classification model for fault detection in electronic circuits. A Sallen-Key band-pass filter was used as the circuit under test (CUT), as soft fault classification in this type of circuit is particularly challenging. This study demonstrates that it is possible to accurately predict faults in circuits similar to the one analyzed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102482"},"PeriodicalIF":2.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient high dimensional yield analysis for SRAM circuits via stack model and adaptive sampling 基于堆叠模型和自适应采样的SRAM电路高效高维良率分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-08 DOI: 10.1016/j.vlsi.2025.102477

Kaijie Li , Liang Pang , Xudong Zhang , Yutao Miao , Yushi Zhang

引用次数: 0

Development of slope detection ASIC for on-chip current sensing in voltage converters 用于电压变换器片上电流传感的斜率检测专用集成电路的研制

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-07 DOI: 10.1016/j.vlsi.2025.102471

Richard Ravasz, Viera Stopjakova, David Maljar, Daniel Arbet, Lukas Nagy, Martin Kovac

引用次数: 0

A hybrid entropy source scheme for true random number generator 真随机数生成器的混合熵源方案

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-07 DOI: 10.1016/j.vlsi.2025.102473

Zhaoxiong Guan, Mingxin Liu, Jinqiang Xu, Cong Lin

引用次数: 0

ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search 基于神经架构搜索的近似神经网络加速器软硬件协同设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-07-03 DOI: 10.1016/j.vlsi.2025.102469

Ying Wu, Zheyu Yan, Xunzhao Yin, Lenian He, Cheng Zhuo

{"title":"ANAS: Software–hardware co-design of approximate neural network accelerators via neural architecture search","authors":"Ying Wu, Zheyu Yan, Xunzhao Yin, Lenian He, Cheng Zhuo","doi":"10.1016/j.vlsi.2025.102469","DOIUrl":"10.1016/j.vlsi.2025.102469","url":null,"abstract":"<div><div>Deep Neural Networks (DNNs) are prevalent solutions for perception tasks, with energy efficiency being particularly critical for deployment on edge platforms. Various studies have proposed efficient DNN edge deployment solutions; however, an important aspect – approximate computing – has been overlooked. Current research primarily focuses on designing approximate circuits for specific DNN models, neglecting the influence of DNN architecture design. To address this gap, this paper proposes a software–hardware co-exploration framework for approximate DNN accelerator design that jointly explores approximate multipliers and neural architectures. This framework, termed Approximate Neural Architecture Search (ANAS), tackles two main challenges: (1) efficiently evaluating the impact of approximate multipliers on application performance and accelerator design for each sample, and (2) effectively navigating a large design space to identify optimal configurations. The framework employs a recurrent neural network-based reinforcement learning algorithm to identify an optimal approximate multiplier-DNN architecture pair that balances DNN accuracy and hardware cost. Experimental results demonstrate that ANAS achieves comparable accuracy while reducing energy consumption and latency by up to 40% compared to state-of-the-art NAS-based methods.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102469"},"PeriodicalIF":2.2,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144556815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0