Low-cost compression architecture based on extended DCT algorithm

Abstract

This paper introduces a low-power, hardware-efficient 2D-DCT architecture aimed at image and video encoding. The architecture implements an optimized Cordic-Loeffler algorithm, which reduces area cost, power consumption, and accelerates the encoding process. The improvement in the Cordic algorithm is achieved by reducing the large number of iteration sequences. Furthermore, the proposed design integrates the Modified Carry Look-Ahead Adder (MCLA) and the Carry Save Adder (CSA) to minimize arithmetic operations and memory requirements. Experimental results demonstrate that the proposed architecture achieves an efficient average peak signal-to-noise ratio (PSNR), especially for endoscopy image compression, along with a reduction in addition/shift operations compared to other competitive Cordic-DCT algorithms.

The proposed architecture was implemented using Xilinx ISE 13.1 for the Virtex5-FPGA, with an operating frequency of 254.6 MHz and a power consumption of 39 mW at 100 MHz. These results surpass the performance of most previous architectures for Virtex-4/Virtex-5 FPGA implementations. According to performance estimations for ASIC implementation using TSMC 130 nm technology, the proposed design dissipates approximately 4.68 mW at 100 MHz, which is notably lower than that of previous works. Thus, the proposed 2D-DCT architecture is particularly suitable for low-power, high-quality codecs, making it ideal for battery-powered embedded systems.