Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Anish Paul , Siya Sharma , Kulbhushan Sharma
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Abstract

As SRAM cells are scaled down to advanced technology nodes, their sensitivity to radiation-induced soft errors increases significantly, making them less reliable for use in critical environments like aerospace and defense. To address this issue, a new 13-transistor radiation-hardened SRAM cell, called SEFCR-13T, is proposed using 18 nm FinFET technology. The cell uses a feedback-cutting technique and redundant node structure to improve soft-error tolerance while maintaining a balance among power, speed, and area. The SEFCR-13T cell is designed and simulated using Cadence Virtuoso and compared with five existing SRAM cells: Conventional 6T, Hybrid 12T, TRD 9T, RHIRS 12T, and RRS 14T. Key performance parameters such as critical charge, static noise margins (SNM), power consumption, delay, and area were evaluated across a voltage range of 0.6 V–1.0 V. At 0.7 V, the proposed SEFCR 13T shows the highest critical charge of 3.67 fC, which is 2.65 × higher than the 6T SRAM and 1.2 × higher than RHIRS 12T. It also achieves a write SNM improvement of up to 2.95 × and read SNM improvement of 2.67 × compared to the 6T cell. Read and write delays are reduced by 2.5 × and 1.8 × , respectively, while read power is reduced by 2.4 × . The proposed design also achieves the highest overall figure of merit (FOM), 17 × better than 6T SRAM. These results show that the proposed cell provides excellent improvement in soft-error resistance and overall stability, making it a strong candidate for reliable memory design in radiation-prone and low-power applications.
基于FinFET 18nm技术的软误差弹性13T SRAM架构设计
随着SRAM单元缩小到先进的技术节点,它们对辐射引起的软误差的敏感性显着增加,使它们在航空航天和国防等关键环境中使用的可靠性降低。为了解决这个问题,提出了一种新的13晶体管抗辐射SRAM单元,称为SEFCR-13T,采用18nm FinFET技术。该单元采用反馈切割技术和冗余节点结构来提高软误差容忍度,同时保持功率、速度和面积之间的平衡。使用Cadence Virtuoso对SEFCR-13T单元进行了设计和仿真,并与现有的五种SRAM单元进行了比较:常规6T、混合12T、TRD 9T、RHIRS 12T和RRS 14T。关键性能参数如临界电荷、静态噪声裕度(SNM)、功耗、延迟和面积在0.6 V - 1.0 V电压范围内进行了评估。在0.7 V下,SEFCR 13T显示出最高的临界电荷为3.67 fC,比6T SRAM高2.65倍,比rirs 12T高1.2倍。与6T单元相比,它还实现了高达2.95倍的写SNM改进和2.67倍的读SNM改进。读时延降低2.5倍,写时延降低1.8倍,读功耗降低2.4倍。提出的设计还实现了最高的总体性能(FOM),比6T SRAM好17倍。这些结果表明,所提出的电池在抗软误差和整体稳定性方面提供了出色的改进,使其成为辐射易发和低功耗应用中可靠存储器设计的有力候选者。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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