Integration-The Vlsi Journal最新文献_第10页

Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS 面向NIDS的基于前缀的高能效高通量模式匹配技术

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102310

Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.

{"title":"Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS","authors":"Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.","doi":"10.1016/j.vlsi.2024.102310","DOIUrl":"10.1016/j.vlsi.2024.102310","url":null,"abstract":"<div><div>Intrusion Detection System (IDS) is a type of packet filtering that ensures network security by analyzing the packets flowing through the network and detecting any malicious pattern(s) present in them. In signature-based NIDS, pattern matching is the critical step as it determines the system’s performance. The throughput of the system, inherently, relies on the delay required to match an input pattern. Hardware-based high-speed pattern matching algorithms are popularly used to speed up the pattern matching process and improve the system’s performance. Ternary Content Addressable Memory (TCAM) is one such memory in which the input pattern is simultaneously launched on all the match lines. Since all the match lines and search lines are activated at a given instance, the power consumed per search is extremely high. To address this issue, this paper proposes an approach in which the match is carried out with an n-bit prefix of the input pattern that enables a smaller TCAM unit, which contains the patterns having this prefix. A significant improvement in energy is observed since a single TCAM segment is enabled for a single search. The results are compared with existing solutions, and energy improvement of 96.1% is observed with worst case and best case throughput of <span><math><mrow><mn>17</mn><mi>G</mi><mi>b</mi><mi>p</mi><mi>s</mi></mrow></math></span> and <span><math><mrow><mn>148</mn><mi>G</mi><mi>b</mi><mi>p</mi><mi>s</mi></mrow></math></span>, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102310"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries 采用虚拟样机和变形测试对嵌入式图形库的硬件/软件栈进行验证

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102320

Christoph Hazott, Florian Stögmüller, Daniel Große

{"title":"Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries","authors":"Christoph Hazott, Florian Stögmüller, Daniel Große","doi":"10.1016/j.vlsi.2024.102320","DOIUrl":"10.1016/j.vlsi.2024.102320","url":null,"abstract":"<div><div>Embedded graphics libraries are part of the <em>Firmware</em> (FW) of embedded systems and provide complex functionalities optimized for specific hardware. After unit testing of embedded graphics libraries, integration testing is a significant challenge, in particular since the hardware is needed to obtain the output image as well as the inherent difficulty in defining the reference result. In this paper, we present a novel approach focusing on integration testing of embedded graphic libraries. We leverage <em>Virtual Prototypes</em> (VPs) and integrate them with <em>Metamorphic Testing</em> (MT). <em>Metamorphic Testing</em> (MT) is a software testing technique that uncovers faults or issues in a system by exploring how its outputs change under predefined input transformations, without relying on explicit oracles or predetermined results. In combination with virtualizing the displays in VPs, we even eliminate the need for physical hardware. This allows us to develop a <em>Metamorphic Testing</em> (MT) framework automating the verification process. In our evaluation, we demonstrate the effectiveness of our <em>Metamorphic Testing</em> (MT) framework. On an extended RISC-V <em>Virtual Prototype</em> (VP) for the GD32VF103VBT6 platform, we found 15 distinct bugs for the widely used TFT_eSPI embedded graphics library, confirming the strength our approach. We finish the evaluation of our <em>Metamorphic Testing</em> (MT) approach by discussing the achieved structural coverage for function, line and branch coverage.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102320"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The art of temporal decoupling 时间解耦的艺术

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102314

Niko Zurstraßen , Ruben Brandhofer , José Cubero-Cascante , Nils Bosbach , Lukas Jünger , Rainer Leupers

{"title":"The art of temporal decoupling","authors":"Niko Zurstraßen , Ruben Brandhofer , José Cubero-Cascante , Nils Bosbach , Lukas Jünger , Rainer Leupers","doi":"10.1016/j.vlsi.2024.102314","DOIUrl":"10.1016/j.vlsi.2024.102314","url":null,"abstract":"<div><div>Virtual Platforms (VPs) and Full-System Simulators (FSSs) are essential tools in modern Multiprocessor System on A Chip (MPSoC) development. Over the past two decades, the speed of these simulations has not kept pace with the increasing complexity of the systems being simulated, highlighting the need for faster simulation techniques. One widely used approach is <em>Temporal Decoupling (TD)</em>, which allows parts of the simulation to run unsynchronized with the rest of the system for a period called the quantum. While a larger quantum improves simulation performance by reducing the number of synchronization and context switches, it also raises the risk of causality errors, leading to inaccuracies. Consequently, users of TD simulations may struggle to find the optimal quantum that balances accuracy and performance. In practice, the quantum is often chosen based on empirical knowledge, which, though sometimes effective, lacks a solid theoretical basis. This work addresses this gap by offering analytical estimations and deeper insights into the effects of TD. We also validate the proposed models using TD simulations in SystemC and gem5.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102314"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit 一种基于视频编码电路的无额外硬件资源开销的超频时钟软件PUF电路

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-09 DOI: 10.1016/j.vlsi.2024.102319

Tengfei Yuan , Pengjun Wang , Yuejun Zhang , Ziyu Zhou

{"title":"An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit","authors":"Tengfei Yuan , Pengjun Wang , Yuejun Zhang , Ziyu Zhou","doi":"10.1016/j.vlsi.2024.102319","DOIUrl":"10.1016/j.vlsi.2024.102319","url":null,"abstract":"<div><div>—Physical unclonable function (PUF) as an emerging hardware security primitive has caused extensive research by scholars. PUF extracts unclonable fingerprint information from intrinsic changes in the circuit during operation. However, conventional PUFs usually adopt the dedicated circuit structure to generate random, non-clonable responses, which require additional hardware resource overhead. This article proposes a software PUF (SPUF) based on the video encoding circuit in response to the above issues. SPUF causes abnormal operation of the encoding circuit by applying an overclocking clock. A response key with circuit characteristics is generated by exploiting the response to timing path dependence. Primarily, the video coding circuit, which is part of the open-source H265 IP Core, is taken as the PUF circuit carrier. Secondly, after analyzing the timing path of the encoding circuit, an overclocking signal is selected according to the timing path to put the circuit in abnormal operating mode. Then, unclonable random data is generated while completing video encoding and compression. Next, the response data is obfuscated by gray encoding and XOR operation to improve the responses' reliability further. Finally, a both-way encrypted lightweight authentication protocol is constructed. Encrypting the video stream with SPUF responses and random numbers enables bi-directional encrypted transmission between the device and the server. The test results show that the proposed SPUF passes the NIST test with a uniqueness of 48.87 %. The autocorrelation coefficient is 0.0204 at 95 % confidence, showing good randomness and uniqueness.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102319"},"PeriodicalIF":2.2,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nested chopper instrument amplifier with noise modulation for physiological signal sensing 带噪声调制的嵌套斩波仪器放大器，用于生理信号传感

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-07 DOI: 10.1016/j.vlsi.2024.102332

Bo Liu, Dong Zhang, Tianyu Liu, Kai Li, Jinchan Wang, Jun Wang

引用次数: 0

SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application siaa：基于显著输入提取的误差优化近似加法器，用于误差弹性应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-07 DOI: 10.1016/j.vlsi.2024.102317

Lalit Bandil, Bal Chand Nagar

{"title":"SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application","authors":"Lalit Bandil, Bal Chand Nagar","doi":"10.1016/j.vlsi.2024.102317","DOIUrl":"10.1016/j.vlsi.2024.102317","url":null,"abstract":"<div><div>This paper presents a new approximate adder design for error-resilient applications, focusing on optimizing errors while maintaining good energy efficiency. The proposed Significant Input Extraction-based Approximate Adder (SIEAA) employs a technique to dynamically identify the significant bits of the input operands and process them through a reduced-width exact adder, allowing for controlled error propagation. This approach improves overall computational accuracy by reducing the mean error distance (MED), resulting in up to 57% lower mean relative error distance (MRED) and normalized MED (NMED). The SIEAA is designed using Verilog-HDL and implemented on an Artix7 FPGA (XC7A35T-1CPG236C). Comprehensive performance analysis reveals that the SIEAA is approximately 1.3 times faster and consumes 37% less power than conventional adders. A trade-off analysis of accuracy versus hardware efficiency demonstrates the SIEAA’s effectiveness over existing approximate adders. An image quantization application using K-means clustering further validates the proposed design’s efficacy in producing good-quality results.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102317"},"PeriodicalIF":2.2,"publicationDate":"2024-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictor Eh-DRVP：在基于超图像的DRV预测器中结合放置和全局路由数据

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-06 DOI: 10.1016/j.vlsi.2024.102309

Sheiny Fabre Almeida , Renan Netto , Tiago Augusto Fontana , Erfan Aghaeekiasaraee , Upma Gandhi , Aysa Fakheri Tabrizi , José Luís Güntzel , Laleh Behjat , Cristina Meinhardt

引用次数: 0

Graph neural network based cell library characterization method for fast design technology co-optimization 基于图神经网络的细胞库表征方法用于快速设计技术协同优化

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-05 DOI: 10.1016/j.vlsi.2024.102316

Tianliang Ma, Guangxi Fan, Xuguang Sun, Kain Lu Low, Leilai Shao

{"title":"Graph neural network based cell library characterization method for fast design technology co-optimization","authors":"Tianliang Ma, Guangxi Fan, Xuguang Sun, Kain Lu Low, Leilai Shao","doi":"10.1016/j.vlsi.2024.102316","DOIUrl":"10.1016/j.vlsi.2024.102316","url":null,"abstract":"<div><div>Design technology co-optimization (DTCO) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTCO flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process–voltage–temperature (PVT) corners, technology parameters and aging effects. Validation with 512 unseen corners and over one million test data points shows accurate predictions of delay, power, and other cell metrics for 37 types of cells and a speed-up of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error <span><math><mo>≤</mo></math></span>3.0 ps for WNS, percentage errors <span><math><mo>≤</mo></math></span>0.60% for leakage power, and <span><math><mo>≤</mo></math></span>0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1%–3% improvement.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102316"},"PeriodicalIF":2.2,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electronically tunable MOSFET-C only meminductor emulator and its application 电子可调谐MOSFET-C记忆电感仿真器及其应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-04 DOI: 10.1016/j.vlsi.2024.102318

Aashish Kumar, Shireesh Kumar Rai

引用次数: 0

APoX-M: Accelerate deep point cloud analysis via adaptive graph construction APoX-M：通过自适应图构建加速深度点云分析

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-03 DOI: 10.1016/j.vlsi.2024.102313

Lei Dai , Shengwen Liang , Ying Wang , Huawei Li , Xiaowei Li

引用次数: 0