Integration-The Vlsi Journal最新文献

{"title":"Nature inspired algorithm based design of near ideal fractional order low pass Chebyshev filters and their realization using OTAs and CCII","authors":"Ritu Daryani,&nbsp;Bhawna Aggarwal","doi":"10.1016/j.vlsi.2024.102185","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102185","url":null,"abstract":"<div><p>Fractional order filters offer greater freedom of design and a precise control over stopband attenuation in electronic circuits and systems. This paper presents the design of a fractional order low pass Chebyshev filter (FOLCF) that achieves near-ideal response characteristics. The methodology introduced utilizes metaheuristic optimization methods, including particle swarm optimization, firefly algorithm, and grey wolf optimization. These techniques are employed to precisely adjust the filter coefficients for the orders (1+α), (2+α), and (3+α). The adjustment is carried out by comparing the desired behaviour of the FOLCF with generalized fractional order low pass transfer functions. Throughout these instances, the parameter α is varied within the range of (0, 1). The designed filters are then tested and compared on the basis of various factors. Simulation results demonstrate that the designed filters closely follow the behaviour of an ideal Chebyshev filter with maximum passband and stopband magnitude errors being −31.93 dB and −52.74 dB respectively for (1+α) order filters. These values for (2+α) and (3+α) order FOLCF have been observed to be −30.04 dB and −55.91 dB; −17.72 dB and −49.52 dB respectively. Furthermore, it has been observed that the proposed work outperforms existing state-of-the-art approaches in various aspects, including magnitude error, stopband attenuation, and cut-off frequency. The stability of the designed filters has been verified through stability analysis. Additionally, practical feasibility of the proposed FOLCF is demonstrated through SPICE simulations for α = [0.2,0.5,0.8] using second generation current conveyor (CCII) and operational transconductance amplifier (OTA) based topologies while approximating the constant phase element using fifth order continued fraction expansion. The SPICE implementations closely follow the behaviour of ideal filter with −48.67 dB and −62.8 dB as mean square errors for CCII and OTA circuits respectively, showcasing the proposed filters' superiority and practical applicability in advanced electronic design.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140320927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space","authors":"Bowen Jiang ,&nbsp;Liang Pang ,&nbsp;Feng Liu","doi":"10.1016/j.vlsi.2024.102189","DOIUrl":"10.1016/j.vlsi.2024.102189","url":null,"abstract":"<div><p>In low-power designs, the SRAM performance suffers from the process variation. Statistical analysis for the yield of circuit block (e.g., static random-access memory) is extremely time-consuming due to the expensive simulations since the variation space is high-dimensional. In this paper, we construct a mixed neural network to substitute the simulation. We present <em>Mixer</em>. It mainly contains two types of layers: one with regularized sub-radial basis function networks (sub-RBFs) applied independently to extract the effects on circuit performance of the subsets of input process variables, and the other one with multi-layer perceptron (MLP) applied to learn the connection of these extracted effects. When trained with small datasets of high dimension generated from 28 nm memory circuits, our Mixer shows competitive accuracy and efficiency compared with other state-of-the-art models.*</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140400072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications","authors":"Lokesh Soni,&nbsp;Neeta Pandey","doi":"10.1016/j.vlsi.2024.102187","DOIUrl":"10.1016/j.vlsi.2024.102187","url":null,"abstract":"<div><p>A single-sided Schmitt-trigger driven 10-transistor (ST 10T) static random access memory cell (SRAM) exhibiting lower power consumption, better read and write access time, improved hold and write stability are presented. Using a Schmitt-trigger inverter and a power gating approach, it has better read and write access time and stability. The single bitline structure with stacking effect lowers the proposed cell’s leakage power. The proposed ST 10T cell has a maximum reduction in power consumption of up to 9667.52 times than the considered structure. Furthermore, improvements in write ability and hold stability of up to 1.62 and 1.17 times respectively, are obtained over compared SRAM cells. The cell reduces read and write access times by up to 1.66 and 45.85 times, respectively. The Monte-Carlo (MC) simulations demonstrate the proposed cell’s resilient performance. The simulation is performed using Cadence Virtuoso GPDK 45 nm CMOS technology.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140282192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm","authors":"Aminur Rahaman,&nbsp;Abhijit Chandra","doi":"10.1016/j.vlsi.2024.102188","DOIUrl":"10.1016/j.vlsi.2024.102188","url":null,"abstract":"<div><p>The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140282208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Qualitative data augmentation for performance prediction in VLSI circuits","authors":"Prasha Srivastava,&nbsp;Pawan Kumar,&nbsp;Zia Abbas","doi":"10.1016/j.vlsi.2024.102186","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102186","url":null,"abstract":"<div><p>Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140181031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Placement legalization for heterogeneous cells of non-integer multiple-heights","authors":"Jooyeon Jeong,&nbsp;Taewhan Kim","doi":"10.1016/j.vlsi.2024.102177","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102177","url":null,"abstract":"<div><p>It is intuitively clear that a circuit to be implemented by selectively utilizing standard cells of various non-integer multiple-heights (NIMH) (e.g., mixed use of 6-track, 7.5-track, and 9-track cells) is able to provide a better opportunity in optimizing power, performance, and area over that by using cells of single-height only or of integer multiple-heights only. However, from the cell placement legalization point of view, the issues to be addressed for placement legalization on NIMH designs are very complex. And this paper primarily focuses on introducing novel ideas for row placement when utilizing NIMH cells, which involves determining the row pattern. The most inter-dependent and critical tasks, which are rather unique to the NIMH cell placement legalization problem, are (<em>task 1</em>) for the cells of the same height, distributing and assigning them to a set of distinct rows on a die and (<em>task 2</em>) determining the location of the rows containing cells of the same height. We solve the legalization problem by, starting from an initial row placement, iteratively solving the two tasks by formulating <em>task 1</em> into an instance of row-capacity constrained network flow problem, followed by solving <em>task 2</em> which leads to an optimal vertical displacement of the cells in the rows. Meanwhile, through experiments, it is shown that our network flow driven global cell assignment to rows for NIMH cell placement problem tightly linking the optimal determination of row location is able to reduce the total amount of cell displacements from the global (initial) placement by 9.5% and 51.2% in comparison with that produced by a greedy approach and the conventional state-of-the-art NIMH cell placement legalization method, respectively.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140096026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Re-configurable parallel Feed-Forward Neural Network implementation using FPGA","authors":"Mohamed El-Sharkawy ,&nbsp;Miran Wael ,&nbsp;Maggie Mashaly ,&nbsp;Eman Azab","doi":"10.1016/j.vlsi.2024.102176","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102176","url":null,"abstract":"<div><p>This paper proposes a novel hardware architecture for a Feed-Forward Neural Network (FFNN) with the objective of minimizing the number of execution clock cycles needed for the network’s computation. The proposed architecture depends mainly on using two physical layers that are multiplexed and reused during the computation of the FFNN to achieve an efficient parallel design. Two physical layers are designed to handle the computation of different sizes of Neural Networks (NN). The proposed FFNN architecture hardware resources are independent of the NN’s number of layers, instead, they depend only on the number of neurons in the largest layer. This versatile architecture serves as an accelerator in Deep Neural Network (DNN) computations as it exploits parallelism by making the two physical layers work in parallel through the computations. The proposed implementation was implemented with 18-bit fixed point representation reaching 200 MHz clock speed on a Spartan7 FPGA. Furthermore, the proposed architecture achieves a lower neuron computation factor compared to previous works in the literature.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140069565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity","authors":"Saurabh Dhiman,&nbsp;Hitesh Shrimali","doi":"10.1016/j.vlsi.2024.102175","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102175","url":null,"abstract":"<div><p>The paper proposes an ameliorated methodology to minimize the effect of charge injection over a wide input common-mode range. Instead of a conventional single dummy switch compensation <span>[1]</span>, the multi-dummy switches are proposed and employed to eradicate the injected charge on to the sampling capacitor. A detailed methodology is presented to compensate the charge injection in a MOS switch. The closed-form equations are derived mathematically to substantiate the proposed technique. For the proof-of-concept, a track-and-hold (T/H) stage has been simulated in <span><math><mrow><mn>0</mn><mo>.</mo><mn>18</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> CMOS technology with the proposed technique for a 10-bit resolution. The proposed technique based T/H stage exhibits the spurious free dynamic range (SFDR) of 62.6 dB, effective number of bits (ENOB) of 9.36, peak input-referred third-order intercept point (IIP3) of 13.02 dBm and an input-referred 1 dB compression point (P<span><math><msub><mrow></mrow><mrow><mtext>1dB</mtext></mrow></msub></math></span>) of 3.8 dBm at 1.074 MHz input frequency, sampled at 100 MSa/s. The performance of the proposed method is compared with the existing single dummy switch compensation method where our technique shows 88.8% compensation in minimizing the charge injection error and 272% improvement in dynamic linearity. Moreover, the presented technique quantifies 9<span><math><mo>×</mo></math></span> improvement in mean percentage error (MPE) when simulated across the various process corners and rail-to-rail input common-mode voltage.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140042369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Double laser-faults based PFA on cryptographic circuits with algebraic analysis","authors":"Xue Gong ,&nbsp;Ao Shen ,&nbsp;Tianxiang Feng ,&nbsp;Guorui Xu ,&nbsp;Shize Guo ,&nbsp;Fan Zhang","doi":"10.1016/j.vlsi.2024.102174","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102174","url":null,"abstract":"<div><p>Cryptographic algorithms have been employed in a variety of fields as the primary method to protect information security. The security of a cryptographic algorithm is closely related to its operating environment and physical devices. Algebraic Persistent Fault Analysis (APFA) is a new fault analysis method for block ciphers proposed in CHES 2022, which utilizes the fault that persists in encryptions and introduces algebraic analysis in the fault analysis step. In the fault injection step, as the transistors of the integrated circuit are getting smaller and tighter, even high-precision devices may cause more than one fault per injection. However, more faults may lead to a more efficient attack in the fault analysis step. In this paper, APFA for double faults is proposed, which can deal with the double faults model and reduce the number of required ciphertexts. The practicality of our fault injection is validated by laser fault injection experiments on the SRAM embedded in an ATmega163L microcontroller. The effectiveness of our fault analysis is proven by successfully recovering the key of PRESENT-128 and AES-128. The number of ciphertexts needed for key recovery is reduced by 46% compared to PFA with a single fault.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140062641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"gm/ID methodology applied to ring oscillators","authors":"Adán Torralba-Ayance,&nbsp;Alejandro Díaz-Sánchez","doi":"10.1016/j.vlsi.2024.102173","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102173","url":null,"abstract":"<div><p>This work presents a ring oscillator design flow that calculates the transistor’s dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span> methodology, and the square root of the delay <span><math><mi>K</mi></math></span>. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140042370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}