Integration-The Vlsi Journal最新文献_第9页

Design of novel low cost triple-node-upset self-recoverable hardened latch 设计新型低成本三节点嵌入式可自动恢复加固闩锁

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-24 DOI: 10.1016/j.vlsi.2024.102199

Hui Xu , Shuo Zhu , Ruijun Ma , Zhengfeng Huang , Huaguo Liang , Haojie Sun , Chaoming Liu

引用次数: 0

Ensemble learning model for effective thermal simulation of multi-core CPUs 多核 CPU 有效热模拟的集合学习模型

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-24 DOI: 10.1016/j.vlsi.2024.102201

Lin Jiang , Anthony Dowling, Yu Liu, Ming-C. Cheng

{"title":"Ensemble learning model for effective thermal simulation of multi-core CPUs","authors":"Lin Jiang , Anthony Dowling, Yu Liu, Ming-C. Cheng","doi":"10.1016/j.vlsi.2024.102201","DOIUrl":"10.1016/j.vlsi.2024.102201","url":null,"abstract":"<div><p>An ensemble data-learning approach based on proper orthogonal decomposition (POD) and Galerkin projection (EnPOD-GP) is proposed for thermal simulations of multi-core CPUs to improve training efficiency and the model accuracy for a previously developed global POD-GP method (GPOD-GP). GPOD-GP generates one set of basis functions (or POD modes) to account for thermal behavior in response to variations in dynamic power maps (PMs) in the entire chip, which is computationally intensive to cover possible variations of all power sources. EnPOD-GP however acquires multiple sets of POD modes to significantly improve training efficiency and effectiveness, and its simulation accuracy is independent of any dynamic PM. Compared to finite element simulation, both GPOD-GP and EnPOD-GP offer a computational speedup over 3 orders of magnitude. For a processor with a small number of cores, GPOD-GP provides a more efficient approach. When high accuracy is desired and/or a processor with more cores is involved, EnPOD-GP is more preferable in terms of training effort and simulation accuracy and efficiency. Additionally, the error resulting from EnPOD-GP can be precisely predicted for any random spatiotemporal power excitation.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0167926024000658/pdfft?md5=1bfea626d6bed7a5cf9433aa649eaf0a&pid=1-s2.0-S0167926024000658-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140783197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain 基于协同设计的 FPGA 实现变换域高效新型语音超混沌密码系统

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-23 DOI: 10.1016/j.vlsi.2024.102197

Mohamed Salah Azzaz, Redouane Kaibou, Bachir Madani

{"title":"Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain","authors":"Mohamed Salah Azzaz, Redouane Kaibou, Bachir Madani","doi":"10.1016/j.vlsi.2024.102197","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102197","url":null,"abstract":"<div><p>In this paper a new encryption system has been designed and implemented for real-time speech transmission to reduce bandwidth requirements, increase security and minimize residual intelligibility. To guarantee robustness and lightweight computation, the developed cryptosystem has been carried out in the wavelet transform domain based on a hyperchaotic model to generate mask and permutation keys. The cryptographic system has been designed using a hardware-software (HW/SW) co-design approach by developing several IP-cores in a relatively short development time. The performances and security evaluation of the system have been validated through simulation results followed by an experimental validation through the implementation of an encrypted speech signal transmission between two low cost Nexys-4 DDR FPGA platforms, operating in real-time for both wired and wireless communications. Compared to similar works, high performances have been obtained in terms of bandwidth efficiency due to the use of DWT, limited area of FPGA resources, low power consumption and high security level with a large keyspace that is sufficient to resist against brute force attacks. The designed system can be a very useful solution for many real-time secure integrated voice communication systems, multiple communication purposes, military, professional or personal high level of conversations security.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140650478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing code allocation for hybrid on-chip memory in IoT systems 优化物联网系统中混合片上存储器的代码分配

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-20 DOI: 10.1016/j.vlsi.2024.102195

Zhe Sun , Zimeng Zhou , Fang-Wei Fu

{"title":"Optimizing code allocation for hybrid on-chip memory in IoT systems","authors":"Zhe Sun , Zimeng Zhou , Fang-Wei Fu","doi":"10.1016/j.vlsi.2024.102195","DOIUrl":"10.1016/j.vlsi.2024.102195","url":null,"abstract":"<div><p>With the increasing application of IoT devices, the memory subsystem, as the performance and energy bottleneck of IoT systems, has received a lot of attention. One of the keys is on-chip memory which can bridge the performance gap between the CPU and main memory. While many off-the-shelf embedded processors utilize the hybrid on-chip memory architecture containing scratchpad memories (SPMs) and caches, most existing literature ignores the collaboration between caches and SPMs. This paper proposes static SPM allocation strategies for the architecture mentioned above in IoT systems, which try to minimize the overall instruction memory subsystem latency and/or energy consumption. We capture the intra- and inter-task cache conflict misses via a fine-grained temporal cache behavior model. Based on this cache conflict information, we propose an integer linear programming (ILP) algorithm to generate an optimal static function level SPM allocation for system performance. Furthermore, to improve the scalability of the proposed allocation scheme for an enormous task set, we offer the interference factor to calculate the interference impact quantitatively. Then, based on the interference factor, we present two approximate knapsack based heuristic algorithms to provide near optimal static allocation schemes at both function- and basic block-level granularities, which favors fast design space exploration. The experiment results demonstrate that the proposed solution achieves a 30.85% improvement in memory performance, and up to 31.39% reduction in energy consumption, compared to the existing SPM allocation scheme at the function level. In addition, the proposed basic block level allocation algorithm shows better performance than our function level allocation algorithm and other basic block level allocation algorithm.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140794438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A memristive neural network with features of asymmetric coexisting attractors and large-scale amplitude control 具有非对称共存吸引子和大规模振幅控制特征的记忆神经网络

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-15 DOI: 10.1016/j.vlsi.2024.102196

Yu Xie, Qiang Lai

引用次数: 0

Corrigendum to “On minimizing charge injection error using multi-dummy switches with enhanced linearity” [Integration volume 97 (2024) 102175] 关于使用线性度更高的多假开关尽量减小电荷注入误差"[《集成》第 97 (2024) 102175 卷]更正

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-14 DOI: 10.1016/j.vlsi.2024.102194

Saurabh Dhiman, Hitesh Shrimali

引用次数: 0

An enhanced logistic chaotic map based tweakable speech encryption algorithm 基于逻辑混沌图的增强型可调整语音加密算法

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-04 DOI: 10.1016/j.vlsi.2024.102192

Herbadji Djamel , Abderrahmane Herbadji , Ismail haddad , Hichem Kahia , Aissa Belmeguenai , Nadir Derouiche

{"title":"An enhanced logistic chaotic map based tweakable speech encryption algorithm","authors":"Herbadji Djamel , Abderrahmane Herbadji , Ismail haddad , Hichem Kahia , Aissa Belmeguenai , Nadir Derouiche","doi":"10.1016/j.vlsi.2024.102192","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102192","url":null,"abstract":"<div><p>This work aims to improves the chaotic behavior of classical logistic chaotic system for voice encryption. In this study, the classical chaotic system was enhanced. This enhanced map has many advantages like a wider chaotic range, more unpredictable, and better ergodicity than many existing chaotic maps (i.e. including 1D and 2D maps). The effectiveness of the improved chaotic system was verified by the bifurcation diagram, performing NIST SP 800-22 and Lyapunov exponent. On this basis, an efficient tweakable voice encryption algorithm was proposed to protect the security of digital voice transmission. The proposed scheme is based on the speech signal being pre-processed to automatically remove silent or voiceless segments, resulting in the extraction of relevant parts of speech for encryption. This leads to a significant reduction in both computing time and resources requirements, as well as the confusion-diffusion architecture. With the aid of the tweak, where each original voice has multiple different encrypted voices using the same secret key which saves time and makes the cost lower compared to changing the key to the proposed scheme. These features make the proposed speech encryption algorithm suitable for real-time communication. In this manner, it is demonstrated that our encryption system effectively withstands known/chosen plaintext attacks. The experimental results demonstrate that the proposed algorithm can withstand several types of attacks through voice encryption. The research results shed new light on the data security in the transmission of voices.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140535665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing cell delay accuracy in post-placed netlists using ensemble tree-based algorithms 利用基于集合树的算法提高后置网表中单元延迟的准确性

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-01 DOI: 10.1016/j.vlsi.2024.102193

Yassine Attaoui , Mohamed Chentouf , Zine El Abidine Alaoui Ismaili , Aimad El Mourabit

引用次数: 0

DAFA: Dynamic approximate full adders for high area and energy efficiency DAFA：实现高面积和能效的动态近似全加法器

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-04-01 DOI: 10.1016/j.vlsi.2024.102191

Yavar Safaei Mehrabani , Reza Faghih Mirzaee

{"title":"DAFA: Dynamic approximate full adders for high area and energy efficiency","authors":"Yavar Safaei Mehrabani , Reza Faghih Mirzaee","doi":"10.1016/j.vlsi.2024.102191","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102191","url":null,"abstract":"<div><p>As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140535994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new die-level flexible design-for-test architecture for 3D stacked ICs 用于三维堆叠集成电路的新型裸片级灵活设计测试架构

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-03-26 DOI: 10.1016/j.vlsi.2024.102190

Qingping Zhang , Wenfa Zhan , Xiaoqing Wen

引用次数: 0