An efficient XOR-free architecture for successive cancellation polar decoding

This paper presents a novel method for implementing an XOR-Free architecture for successive cancellation (SC) decoding in polar codes. From the hardware implementation perspective, the primary goal of this paper is to replace the XOR processing unit, which consumes significant dynamic power and processing time. The proposed architecture completely replaces the XOR operations of the SC polar decoder by using combinations of multiplexers and inverters. The proposed XOR-Free decoder retains the same functionality as that of traditional SC polar decoder. A comparative analysis of various SC polar decoders with the XOR-Free polar decoder is also presented. The proposed XOR-Free SC polar decoder is implemented with the Virtex Ultra-Scale FPGA family using AMD Xilinx Vivado. The implemented results reveal that the proposed architecture is more efficient in terms of hardware cost, power consumption, delay, and throughput.