A low power noise tolerant wide fan-in OR logic domino gate

Abstract

In this work, a low power noise tolerant domino gate is designed to reduce the leakage current and enhance the noise margin at optimized delay for wide fan-in OR logic. These improvements in the proposed domino gate have made in two phase. In the first phase, an arrangement, in which transmission gate along with static inverter, is designed to control the conduction of keeper transistor so that dynamic power and noise margin can be reduced and improved simultaneously. In second phase, two transistors having low threshold voltage in the evaluation network are inserted to decrease the subthreshold leakage current at optimized delay. Further, 256-bit wide multiplexer has been designed using the proposed domino gate to test the efficiency over the conventional domino. Thus, it is concluded that proposed domino is capable to design modern superscalar microprocessor, register file and other wide fan-in low power VLSI circuits. According to the simulation results, this work demonstrates a power consumption decrease of 20 % and 12 % as well as a noise margin improvement of 58 % and 25 % when compared with conventional domino and high speed domino, respectively. The cadence virtuoso EDA tool is used to evaluate and obtain the performance parameters of the designed gate along with existing work for 45 nm CMOS technology.