Integration-The Vlsi Journal最新文献_第8页

Dynamical behaviors of the simple chaotic system with coexisting attractors and its synchronous application 具有共存吸引子的简单混沌系统动力学行为及其同步应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-23 DOI: 10.1016/j.vlsi.2025.102368

Shaohui Yan, Rong Lu, Hanbing Zhang

{"title":"Dynamical behaviors of the simple chaotic system with coexisting attractors and its synchronous application","authors":"Shaohui Yan, Rong Lu, Hanbing Zhang","doi":"10.1016/j.vlsi.2025.102368","DOIUrl":"10.1016/j.vlsi.2025.102368","url":null,"abstract":"<div><div>A simple 3D dissipative chaotic system with coexisting attractors is constructed in this paper. The dynamical behavior of the system is analyzed using numerical simulations of phase space and bifurcation diagrams as the parameters and initial conditions are varied. The amplitude of the state variable can be flexibly controlled by introducing the offset boosting, providing a controllable capability for the system. By analyzing and comparing the complexity, the initial condition with higher complexity is selected and used for synchronization control. The system is then subjected to circuit implementation. Finally, the synchronization of chaotic systems is realized by two synchronization methods, namely backstepping synchronization and finite-time synchronization. And the merits and drawbacks of the two synchronization methods are briefly compared and summarized. In contrast, finite-time synchronization demonstrates good performance, achieving synchronization times of 0.61 s and 0.81 s under different initial conditions. Thus, a circuit simulation for finite-time synchronization is conducted, with results consistent with the numerical simulation outcomes.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102368"},"PeriodicalIF":2.2,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CDA-GC: An effective cache data allocation for garbage collection in flash-based solid-state drives CDA-GC：在基于闪存的固态驱动器中用于垃圾收集的有效缓存数据分配

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-22 DOI: 10.1016/j.vlsi.2025.102359

Keyu Wang , Huailiang Tan , Zaihong He , Jinyou Li , Keqin Li

{"title":"CDA-GC: An effective cache data allocation for garbage collection in flash-based solid-state drives","authors":"Keyu Wang , Huailiang Tan , Zaihong He , Jinyou Li , Keqin Li","doi":"10.1016/j.vlsi.2025.102359","DOIUrl":"10.1016/j.vlsi.2025.102359","url":null,"abstract":"<div><div>In the research of solid-state drive (SSD) performance enhancement, constructing an efficient garbage collection (GC) mechanism is crucial for accelerating device operations and extending their service life, especially in large data processing applications like databases and file systems. Therefore, this paper conducts an in-depth study on the impact of cache management strategies on GC performance and proposes an innovative GC algorithm called Cache Data Allocation GC (CDA-GC). By optimizing data allocation and management within the cache, this algorithm reduces unnecessary data migration during the GC process, thereby improving data processing efficiency and reducing the impact of GC operations on device performance. The core of CDA-GC lies in its innovative cache data management strategy, which can significantly reduce the data migration demands during the GC process. This method not only improves the overall processing performance of SSDs but also reduces the adverse impact of GC activities on device performance by optimizing data access patterns. We implemented and validated the algorithm on the Cosmos+ OpenSSD platform and compared it with existing advanced SSD caching strategies in real-world scenarios. Experimental results show that in database and file system applications, the CDA-GC algorithm can effectively improve performance.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102359"},"PeriodicalIF":2.2,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference 一个2.69 ppm/°C曲率补偿的基于bjt的带隙电压基准

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-21 DOI: 10.1016/j.vlsi.2025.102361

Hamidreza Rashidian , Iman Soltani , Mohammad Maghsoudi

引用次数: 0

Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case 电力电子中的分数阶PI/PD和PID控制器：降压变换器案例

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-21 DOI: 10.1016/j.vlsi.2025.102360

Allan G.S. Sánchez , F.J. Pérez-Pinal

引用次数: 0

Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer 基于混沌的数据安全方法：非相称分数阶Arneodo混沌系统分析及其在微机上的工程应用

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-18 DOI: 10.1016/j.vlsi.2025.102355

Akif Akgül , Mustafa Yaz , Berkay Emi̇n

{"title":"Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer","authors":"Akif Akgül , Mustafa Yaz , Berkay Emi̇n","doi":"10.1016/j.vlsi.2025.102355","DOIUrl":"10.1016/j.vlsi.2025.102355","url":null,"abstract":"<div><div>In this study, the Arneodo chaotic system was designed as an incommensurate fractional-order system, and the equilibrium points, time series, and phase portraits of the system were obtained, while the Lyapunov exponents were calculated. The incommensurate fractional-order system was modeled and simulated on the Nvidia Jetson AGX Orin, and its practical applications were realized with the designed electronic circuit. The chaotic equations were discretized via the Grünwald–Letnikov method, and a random number generator (RNG) based on an embedded system was implemented using the proposed algorithm. The RNG successfully met the criteria of international statistical evaluations, including NIST 800-22, FIPS 140-1, and ENT, thereby serving as a foundation for encryption and steganography algorithms. An original image encryption algorithm based on an embedded system was developed using the incommensurate fractional-order chaotic RNG. Encryption algorithm performance was evaluated through various security analyses, demonstrating the success of the incommensurate fractional-order Arneodo (IFOAR) system in embedded encryption applications. Furthermore, an embedded system-based image steganography algorithm was developed using the designed RNG, providing two-level security. The effectiveness of incommensurate chaotic system in steganography applications has been proved by various security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102355"},"PeriodicalIF":2.2,"publicationDate":"2025-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143288595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high isolation 16–19 GHz down-conversion mixer in 0.18-μm SiGe Bi-CMOS 高隔离16-19 GHz下变频混频器，0.18 μm SiGe Bi-CMOS

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-13 DOI: 10.1016/j.vlsi.2025.102358

Jun-Da Chen, Shan-Yi Cheng

{"title":"A high isolation 16–19 GHz down-conversion mixer in 0.18-μm SiGe Bi-CMOS","authors":"Jun-Da Chen, Shan-Yi Cheng","doi":"10.1016/j.vlsi.2025.102358","DOIUrl":"10.1016/j.vlsi.2025.102358","url":null,"abstract":"<div><div>This paper introduces a novel down-conversion mixer chip explicitly designed for low-orbit satellites operating in the K-band frequency range (16–19 GHz). The chip, fabricated using TSMC's 0.18-μm SiGe Bi-CMOS technology, offers a unique combination of MOS and HBT bipolar junction transistors (BJTs). The double-balanced mixer uses Marchand baluns on the RF and LO ports to convert single-ended signals to differential ones. Transformer coupling between the RF transconductance and LO switching stages ensures excellent isolation and linearity. The proposed series-parallel switching stage effectively increases the switching current at frequencies above 10 GHz and improves the conversion gain at low voltages. The measured results for the proposed mixer demonstrate a power conversion gain of 3.4–4.7 dB with a flat variation of ±0.7 dB and an input third-order intercept point (IIP3) ranging from −1.8 to 0 dBm. These results indicate the performance of the mixer in terms of power gain and linearity. The isolation of RF-to-LO, RF-to-IF, and LO-to-IF are 60, 62, and 30 dB at 19 GHz, respectively, which is crucial for preventing signal interference. The total DC power consumption for 1.1/1 V dual voltage with output buffer is 16.6 mW. The total chip size is 1.11 × 0.843 mm<sup>2</sup>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102358"},"PeriodicalIF":2.2,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparative study of planar stacked integrated transformers for MMICs mmic用平面堆叠式集成变压器的比较研究

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-10 DOI: 10.1016/j.vlsi.2025.102346

Mokhtaria Derkaoui , Yamina Benhadda , Azzedine Hamid

{"title":"Comparative study of planar stacked integrated transformers for MMICs","authors":"Mokhtaria Derkaoui , Yamina Benhadda , Azzedine Hamid","doi":"10.1016/j.vlsi.2025.102346","DOIUrl":"10.1016/j.vlsi.2025.102346","url":null,"abstract":"<div><div>This paper describes the comparative study of different transformer topologies operating for Monolithic Microwave Integrated Circuit (MMIC). Planar stacked square, octagonal and circular coil topologies were studied to illustrate the good performance. The primary and secondary coils had the same dimensions with 1:1 turn ratio. The simplified physical equivalent circuit was demonstrated to evaluate its components values. Transformers prototype were fabricated using a standard 130 nm CMOS process. COMSOL Multiphysics analysis was carried out to show the electromagnetic and thermal behaviour. Simulations show quality factor improvements for the flipped circular topology. The square topology presents a high temperature and losses due to the right angles. The octagonal topology avoid to concentrates the current density in the angles but allows to increase the temperature due to the great number of segments. Measurements of insertion loss and coupling factor on circular topology demonstrate the good agreement with the proposed model. Simulated and measured magnitudes and phases for different outer diameter and width are identical. The results revealed that the planar transformer with the circular topology offers high performances.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102346"},"PeriodicalIF":2.2,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor 基于超低功率线性化FVF的双扩散双差分对晶体管

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-06 DOI: 10.1016/j.vlsi.2025.102345

Ravi Ranjan Kumar, Kulbhushan Sharma

引用次数: 0

A low-power two-step gray-code counter for single-slope ADC in CMOS image sensors 用于CMOS图像传感器单斜率ADC的低功耗两步灰度码计数器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-03 DOI: 10.1016/j.vlsi.2024.102341

Xiaofeng Gu, Sikai Zhong, Xiaoyu Zhong, Taotao Zhou, Wenzhuo Li, Zhiguo Yu

引用次数: 0

All pass transformation based variable digital filter design using low power approximate floating point adder and low power compressor based approximate multiplier 基于全通变换的可变数字滤波器设计采用低功耗近似浮点加法器和基于低功耗压缩器的近似乘法器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-01-03 DOI: 10.1016/j.vlsi.2025.102344

P. Thilagavathi , S. Senthil Kumar , D. Gowthami , A. Sridevi

{"title":"All pass transformation based variable digital filter design using low power approximate floating point adder and low power compressor based approximate multiplier","authors":"P. Thilagavathi , S. Senthil Kumar , D. Gowthami , A. Sridevi","doi":"10.1016/j.vlsi.2025.102344","DOIUrl":"10.1016/j.vlsi.2025.102344","url":null,"abstract":"<div><div>Digital signal processing filters are essential in various applications that require a balance between accuracy, power efficiency, and computational complexity. Variable digital filters (VDF) are increasingly important in signal processing and communication. This manuscript proposes All Pass Transformation dependent Variable Digital Filter using Low Power Approximate Floating Point Adder and Low Power Compressor based Approximate Multiplier (APT-VDF-LP-AFPA-LP-CAM). The proposed APT-VDF-LP-AFPA-LP-CAM overcomes performance limitations by utilizing advanced approximation techniques to enhance speed and reduce power consumption. The LP-AFPA leverages state-of-the-art approximate compound gates to accelerate addition and minimize carry propagation delays, while the LP-CAM employs a divide and conquer method for efficient partial product generation. The proposed approach is simulated using Xilinx ISE 14.5, shows significant improvements with 20.98 %, 12.67 % and 33.76 % reduction in delay and 21.90 %, 31.45 % and 27.45 % decrease in power consumption, and an operating frequency of 210.87 MHz. These advancements outperform existing methods, such as APT-VDF utilizing ternary adder and multiplier (APT-VDF-TA-TM), All-pass digital filters with dual carry select adder (CDF-ESDCSA-TRAF), Power-efficient FIR filters with ESSA and VL-CSKA (ESSA-VL-CSKA). This work underscores the effectiveness of integrating advanced approximation techniques in APT-VDF design, paving the way for future developments in high-speed and low-power digital signal processing applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102344"},"PeriodicalIF":2.2,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0