Integration-The Vlsi Journal最新文献_第8页

Network traffic inspection to enhance anomaly detection in the Internet of Things using attention-driven Deep Learning 利用注意力驱动深度学习增强物联网异常检测的网络流量检测

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-13 DOI: 10.1016/j.vlsi.2025.102398

Mireya Lucia Hernandez-Jaimes , Alfonso Martinez-Cruz , Kelsey Alejandra Ramírez-Gutiérrez , Alicia Morales-Reyes

{"title":"Network traffic inspection to enhance anomaly detection in the Internet of Things using attention-driven Deep Learning","authors":"Mireya Lucia Hernandez-Jaimes , Alfonso Martinez-Cruz , Kelsey Alejandra Ramírez-Gutiérrez , Alicia Morales-Reyes","doi":"10.1016/j.vlsi.2025.102398","DOIUrl":"10.1016/j.vlsi.2025.102398","url":null,"abstract":"<div><div>Anomaly detection methods are being developed to enhance the security of the Internet of Things (IoT) in the healthcare sector, particularly against cyberattacks targeting network vulnerabilities. On the other hand, supervised Machine learning (ML) algorithms have been leveraged because of their potential to handle large amounts of data and identify patterns. However, their effectiveness in identifying unknown attacks is uncertain, and the limited labeled data in the Internet of Medical Things (IoMT) environments challenges the adoption of these methods. In response, unsupervised ML-based anomaly detection methods have been proposed. Unfortunately, their performance remains suboptimal compared to supervised ML and unsupervised Deep Learning (DL) models due to the challenges posed by the heterogeneous nature of IoT data, which complicates the extraction and selection of relevant network traffic features—critical processes to ensure the effectiveness of these methods. To address these challenges, this study proposes a novel attention-driven deep neural network algorithm for network traffic representation, resulting in an improved unsupervised anomaly detection performance of the One-Class Support Vector Machine and performance comparable to current unsupervised DL-based methods. This novel network traffic characterization method relies on just nine generic features and the knowledge of which communication protocols are present or absent by applying principles from two natural language processing techniques. On the CICIoMT2024 dataset, our proposal achieves a precision of 84.43%, a recall of 98.73%, and an F1-score of 91.02%. On the MQTT-IoT-IDS2020 dataset, we achieve 92.14%, 99.17%, and 95.53% of precision, recall, and F1-score, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102398"},"PeriodicalIF":2.2,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143678932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems 基于人工神经网络和混沌系统的新型加密安全伪随机数生成器的设计与FPGA实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-08 DOI: 10.1016/j.vlsi.2025.102388

Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi

{"title":"Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems","authors":"Youcef Alloun , Abdenour Kifouche , Mohamed Salah Azzaz , Mahdi Madani , El-Bay Bourennane , Said Sadoudi","doi":"10.1016/j.vlsi.2025.102388","DOIUrl":"10.1016/j.vlsi.2025.102388","url":null,"abstract":"<div><div>A secure random number generator (RNG) is crucial for cryptography and data protection applications. Many existing approaches employ classical chaotic systems, which have been demonstrated as vulnerable to some attacks. Therefore, this research proposes the design on FPGA of a new pseudo-RNG based on an artificial neural network (ANN) and chaotic systems. Initially, a multi-layer perceptron (MLP) with a hardware friendly activation function (AF) is trained to mimic the behavior of the unified chaotic system (UCS). To mitigate chaos degradation and the difference between the training and the inference, the scheduled sampling technique is adapted and applied to the MLP network. Once the model is well-tuned, its chaotic nature is validated by calculating the Lyapunov exponents and determining the fractal dimension. The pre-trained model based on which an MLP-based Chaotic Pseudo-RNG (MLP-CPRNG) is then implemented on FPGA using VHDL language and Xilinx Vivado design suite. To improve the generator’s output capabilities, a technique named the <span><math><mi>d</mi></math></span>-lagged differencing (<span><math><mi>d</mi></math></span>-LD) is implemented as a part of the MLP-CPRNG. The implemented MLP-CPRNG outperforms the existing works in terms of resource utilization, which makes it suitable for resource-constrained environment. It also offers extended key space and has successfully passed performance tests such as NIST statistical tests, entropy measurement, and correlation analysis. These results highlight the robustness of MLP-CPRNG against brute-force, algebraic and statistical attacks, thus its suitability for embedded cryptographic applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102388"},"PeriodicalIF":2.2,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard CCSDS近地标准的资源高效和超高吞吐量LDPC解码器

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-07 DOI: 10.1016/j.vlsi.2025.102390

Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li

{"title":"Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard","authors":"Lintao Li , Xiaoxia Yao , Yimin Li , Ran Zhu , Jiayi Lv , Hua Li","doi":"10.1016/j.vlsi.2025.102390","DOIUrl":"10.1016/j.vlsi.2025.102390","url":null,"abstract":"<div><div>This paper presents a resource-efficient, ultra-high throughput low density parity check (LDPC) decoder that is suitable for tens of gigabit bits per second satellite communications. To address routing congestion and critical path delay, which are typically caused by the high degree of parallelism in high throughput decoder designs, this work introduces an efficient computation circuit for identifying the two minimum values in the check node update process. Furthermore, a non-uniform quantization method based on mutual information maximization is proposed for log-likelihood ratio (LLR) representation, enabling a more favorable trade-off between decoding performance and implementation complexity. Additionally, the decoder utilizes a pipelined multi-frame parallel scheduling scheme, which significantly boosts throughput with only a slight increase in storage requirements. Finally, the proposed design is implemented and tested on a Xilinx UltraScale+ XCVU13P FPGA. The results show that the decoder achieves a throughput of 76.5Gbps at 8 iterations and 200MHz. This implementation outperforms existing designs, highlighting the innovative and superior nature of our approach.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102390"},"PeriodicalIF":2.2,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant 基于apsamry常数的新型超混沌系统发生器的设计与实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102399

Omer Kocak , Uğur Erkan , Ismail Babaoglu

{"title":"Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant","authors":"Omer Kocak , Uğur Erkan , Ismail Babaoglu","doi":"10.1016/j.vlsi.2025.102399","DOIUrl":"10.1016/j.vlsi.2025.102399","url":null,"abstract":"<div><div>Modern chaotic systems necessitate high levels of randomness and complexity, which can be achieved through adaptable seed functions. This paper proposes a new 2D Apéry chaotic system generator (2D-ACG) based on Apéry numbers to fulfill this need. The 2D-ACG generates various chaotic systems using classical seed functions. The effectiveness and the capabilities of 2D-ACG are demonstrated on three well-known example chaotic maps using pairs of seed functions such as Cos-Cos, Sin-Sin and Cos-Sin. The reliability of chaos metrics, such as the Lyapunov exponent (LE), sample entropy (SE), correlation dimension (CD), Kolmogorov entropy (KE), C0 test, and sensitivity, confirms the chaotic performance of these maps. This is further supported by a comparison with reported 2D chaotic systems. Furthermore, one of the maps derived from 2D-ACG has been implemented into an image encryption algorithm and has successfully passed the cryptanalysis tests. Additionally, the hardware implementation of 2D-ACG has been tested on a field programmable gate array (FPGA), thereby confirming its efficacy. The superior results obtained indicate that the proposed 2D-ACG, with its enhanced diversity and complex structure derived from the Apéry's constant, exhibits higher-performance chaotic characteristics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102399"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143609484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application 一种用于ZigBee应用的低功耗、低pdp双模CML分频器的设计

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102400

Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab

{"title":"Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application","authors":"Lokenath Kundu , Subhanil Maity , Sourav Nath , Gaurav Singh Baghel , Krishna Lal Baishnab","doi":"10.1016/j.vlsi.2025.102400","DOIUrl":"10.1016/j.vlsi.2025.102400","url":null,"abstract":"<div><div>This work presents novel single-ended (Design I and Design II) and double-ended (Design III and Design IV) architectures of 2/3 frequency dividers (FDs) that improve power delay product (PDP) and power consumption. This novel work proposes four kinds of 2/3 dual modulus FDs that are compatible with ZigBee and Bluetooth communication standards. The proposed designs are also tunable for different communication bands and are based on current mode logic (CML) in the 2.4–2.8 GHz PLL application range. The subblocks of 2/3 dual modulus FDs use CML-based latches, XOR gates, and delay cells to achieve the desired functionality. The g<sub>m</sub> over I<sub>d</sub> (g<sub>m</sub>/I<sub>d</sub>) methodology is explored for the optimum design of latches, enabling efficient circuit sizing and enhanced performance. This lowers the total power consumption to 0.6 mW with a power delay product (PDP) of 1 fJ. These proposed designs are post-layout simulated using a TSMC 65 nm CMOS process technology node. These designs are compared with the recent post-layout performances of state-of-the-art works with 30.6 dB of figure of merits (FoM). This work entails statistical analysis (Monte Carlo (MC)) as well as variations in process, supply voltage, and temperature (PVT analysis) in accordance with the AEC-Q100 standard (Grade 1).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102400"},"PeriodicalIF":2.2,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143579833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains 丰富的动态和模拟实现的Hopfield神经网络在整数和分数阶域

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-05 DOI: 10.1016/j.vlsi.2025.102389

Diego S. de la Vega , Jesus M. Munoz-Pacheco , Olga G. Félix-Beltrán , Christos Volos

引用次数: 0

Low test cost adaptive testing method for high yield IC products 低测试成本的高成品率集成电路产品自适应测试方法

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-03-04 DOI: 10.1016/j.vlsi.2025.102401

Yuqi Pan, Huaguo Liang, Junming Li, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu

引用次数: 0

The effect of ECG data variability on side-channel attack success rate in wearable devices 心电数据变异性对可穿戴设备侧信道攻击成功率的影响

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-28 DOI: 10.1016/j.vlsi.2025.102385

Pablo Perez-Tirador , Ruzica Jevtic , Carmen Cabezaolias , Teresa Romero , Abraham Otero , Gabriel Caffarena

{"title":"The effect of ECG data variability on side-channel attack success rate in wearable devices","authors":"Pablo Perez-Tirador , Ruzica Jevtic , Carmen Cabezaolias , Teresa Romero , Abraham Otero , Gabriel Caffarena","doi":"10.1016/j.vlsi.2025.102385","DOIUrl":"10.1016/j.vlsi.2025.102385","url":null,"abstract":"<div><div>As the connectivity and number of health monitoring devices has increased dramatically in recent years, various security issues have become a serious threat to the integrity of patient data. Side-channel attacks are particularly dangerous for these devices because they do not rely on the mathematical complexity of the cryptographic algorithm, but instead exploit physical information leakage. In this work, we analyze electromagnetic and power side-channel attacks on portable electrocardiogram (ECG) monitoring devices. Unlike other work that uses random data, we analyze attacks based on real ECG data and show that the data distribution significantly affects the success rate of the attacks. We build a wearable ECG garment that records a single-lead ECG and sends it to a low-power microcontroller for encryption using AES. The results show that the first-round attack success rate is strongly influenced by the number of bits used to encrypt each ECG sample and the intensity level of the patient’s physical activity. More intense activity produces more artifacts in the ECG that increase the overall signal variability. An increase in variability generally results in an 86% reduction in the number of power samples required for an attack. The final attack also shows a dependence on input variability, but to a lesser extent. Input data with higher variability reduces the number of traces required for this attack by up to 50%, and the attack only becomes unsuccessful in the presence of extremely high levels of noise during the ECG recording. Based on these results, mitigation measures that exploit a change in signal variability are proposed.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102385"},"PeriodicalIF":2.2,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lorenz system manufacturing with a Butterworth filter 用巴特沃斯滤波器制造洛伦兹系统

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-27 DOI: 10.1016/j.vlsi.2025.102386

L.L. Jiménez-Zacarías , I. Campos-Cantón

引用次数: 0

Dynamics analysis and DSP implementation of a new four-dimensional discrete memristor hyperchaotic map 一种新型四维离散忆阻器超混沌映射的动力学分析与DSP实现

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2025-02-25 DOI: 10.1016/j.vlsi.2025.102384

Chenkai Zhang, Huibin Wang, Yiyan Zhang, Lili Zhang, Chunyan Ma

{"title":"Dynamics analysis and DSP implementation of a new four-dimensional discrete memristor hyperchaotic map","authors":"Chenkai Zhang, Huibin Wang, Yiyan Zhang, Lili Zhang, Chunyan Ma","doi":"10.1016/j.vlsi.2025.102384","DOIUrl":"10.1016/j.vlsi.2025.102384","url":null,"abstract":"<div><div>In recent years, discrete memristors have garnered significant interest from the scientific community due to their nonlinear and adaptive properties. These characteristics make them ideal for use as nonlinear elements in generating chaotic oscillations. However, the current research on the discrete memristor chaotic map is still focused on constructing it by coupling first-order discrete memristors, and the research on coupling higher-order discrete memristors is relatively limited. This paper presents a novel four-dimensional discrete memristor hyperchaotic map that is coupled with a second-order discrete memristor. Through numerical simulations, we analyze the bifurcation diagram and Lyapunov index diagram of the new map with the change of coupling coefficient and various control parameters. Our findings indicate that the map exists in a hyperchaotic state and demonstrates the coexistence of multiple attractors under varying initial conditions. This results in a rich tapestry of dynamic behaviors and high complexity. Moreover, we have implemented the memristor chaotic map by DSP platform.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102384"},"PeriodicalIF":2.2,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0