Integration-The Vlsi Journal最新文献

{"title":"A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation","authors":"Tiedong Cheng,&nbsp;Hao Rao,&nbsp;Jinxiang Wei","doi":"10.1016/j.vlsi.2024.102209","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102209","url":null,"abstract":"<div><p>A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the <span><math><mrow><mo>Δ</mo><msub><mi>V</mi><mrow><mi>G</mi><mi>S</mi></mrow></msub></mrow></math></span> of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141091016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection","authors":"Yuhai He ,&nbsp;Jiye Huang ,&nbsp;Yiming Pan","doi":"10.1016/j.vlsi.2024.102208","DOIUrl":"10.1016/j.vlsi.2024.102208","url":null,"abstract":"<div><p>In today’s increasingly complex traffic environment, pedestrian detection has become increasingly important. The Histogram of Oriented Gradients (HOG) algorithm has been proven to be highly efficient in pedestrian detection. This paper proposes a low-resource consumption, high-speed hardware implementation for HOG algorithm. In the case of a slight sacrifice in accuracy, it increases computational speed and reduces resource consumption. Experimental results demonstrate that the implementation achieves a speed of 0.933 pixels per clock cycle and consumes 4117 look-up tables and 4.5 Kbits of block RAMs while its accuracy decreases by 1.2% on the INRIA dataset and by 0.11% on the MIT dataset.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141053099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency","authors":"Jinn-Shyan Wang ,&nbsp;Yu-Hsuan Kuo","doi":"10.1016/j.vlsi.2024.102207","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102207","url":null,"abstract":"<div><p>Previous work has presented a synthesizable design approach to ease the design of an on-chip period-jitter sensor (PJS) with a high resolution. Although the designer of a very large scale integration (VLSI) chip hopes to use this design as an intellectual property (IP), our analysis reveals that this PJS faces key challenges: high power consumption and vulnerability to static PVT and dynamic IR-drop variations. This work develops several design techniques to conquer these challenges at the same time. Taking the PJS IP for monitoring the clock signal in LPDDR4-4266 as a design example, we implement a synthesized 22 nm 2.133 GHz PJS with a resolution of 1.0 ps to verify the design techniques. Post-layout simulation results show that the new design reduces over half of the power while meeting the resolution specification. It passes functional and electrical verification over a broader process variation than the previous design, and the higher variation resiliency assists the synthesizable Verilog code as a soft IP.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140918516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network","authors":"A.N. Busygin ,&nbsp;S. Yu Udovichenko ,&nbsp;A.D. Pisarev ,&nbsp;A.H.A. Ebrahim ,&nbsp;A.A. Gubin","doi":"10.1016/j.vlsi.2024.102203","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102203","url":null,"abstract":"<div><p>A programmable logic device based on a memristor-diode crossbar and CMOS logic has been developed. The crossbar implements NAND logic gates using memristor ratioed logic and CMOS inverters. The digitally controlled peripheral circuit provides digital signals transmission and allows modification and evaluation memristor states in the crossbar. The proposed logic device circuit requires fewer transistors than known analogues and less area on the chip.</p><p>The maximum size of the crossbar in a logic device is estimated by numerical simulation at the level of electrical circuits. The limited size is caused by the degradation of the logic levels voltages in the memristor-diode crossbar. The operability of peripheral circuits as part of a complete electrical circuit of a logic device is demonstrated during the simulation of the execution of logical operations, the processes of modification and evaluation states of individual memristors.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140906697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network","authors":"Liwen Zhang,&nbsp;He Yang,&nbsp;Chen Yang,&nbsp;Jincan Zhang,&nbsp;Jinchan Wang","doi":"10.1016/j.vlsi.2024.102205","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102205","url":null,"abstract":"<div><p>The single-objective and single-parameter optimization method is commonly used in the structure optimization of TSV to improve the transmission characteristics, for which a structure design scheme that simultaneously satisfies multiple target requirements is difficult to obtain. Moreover, the method cannot simultaneously optimize different design parameters. Aiming at the above problems, a global optimization method based on the grey wolf optimization (GWO) algorithm and artificial neural network (ANN) model is proposed. With the presented mixed dielectric coaxial-annular TSV model, firstly six key design parameters A-F are selected as optimization variables by the control variable method. The L₂₅(5⁶) orthogonal experiment is designed for Taguchi analysis and analysis of variance (ANOVA). Then, three prediction models, ANN, support vector machine (SVM), and extreme learning machine (ELM), are developed with the extended orthogonal data as the training sets. It is found that the ANN model performed best. To search for the global optimal solution, the genetic algorithm (GA) and GWO algorithm, combined with the ANN model are applied, respectively. The results show that the GWO algorithm is more successful in solving the problem of falling into the local optimum than GA, and the convergence speed is faster and more stable. After GWO-ANN optimization, the performance of each <em>S</em>-parameter index is greatly improved, <em>S</em>₁₁ reduces by 14.05 dB, <em>S</em>₂₁ increases by 0.33 dB, and <em>S</em>₃₁ reduces by 12.50 dB at 30 GHz.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140948440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency","authors":"Zahra Hashemi,&nbsp;Mostafa Yargholi","doi":"10.1016/j.vlsi.2024.102204","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102204","url":null,"abstract":"<div><p>A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140918517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation","authors":"Yildiran Yilmaz ,&nbsp;Fatih Gül","doi":"10.1016/j.vlsi.2024.102206","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102206","url":null,"abstract":"<div><p>Computer-based machine learning algorithms that produce impressive performance results are computationally demanding and thus subject to high energy consumption during training and testing. Therefore, compact neuro-inspired devices are required to achieve efficiency in hardware resource consumption for the smooth implementation of neural network applications that require low energy and area. In this paper, learning characteristics and performances of the nanoscale titanium dioxide (<span><math><msub><mrow><mi>TiO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>) based synaptic device have been analyzed by implementing it in the hardware-based neural network for digit classification. Our model is experimentally validated by using 32-nm CMOS technology and the results demonstrate that the model provides high computational ability with better accuracy and efficiency in resource consumption with low energy and less area. The proposed model exhibits 20% energy gain and 16.82% accuracy improvement and 18% less total latency compared to the state-of-the-art <span><math><mi>Ag</mi></math></span>:<span><math><mi>Si</mi></math></span> synaptic device-based neural network. Furthermore, when compared to the software-based (i.e., computer-based) implementation of neural networks, our <span><math><msub><mrow><mi>TiO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>-based model not only achieved an impressive accuracy rate of 90.01% on the MNIST dataset but also did so with reduced energy consumption. Consequently, our model, characterized by a low hardware implementation cost, emerges as a promising neuro-inspired hardware solution for various neural network applications. The proposed model has further demonstrated outstanding performance in experiments involving both the MNIST and Fisher’s Iris datasets. On the latter dataset, the model exhibited notable precision (94.5%), recall (91.5%), and an impressive F1-score (92.9%), accompanied by a commendable accuracy rate of 93.04%.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140918518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring BTI aging effects on spatial power density and temperature profiles of VLSI chips","authors":"Sachin Sachdeva,&nbsp;Jincong Lu,&nbsp;Hussam Amrouch ,&nbsp;Sheldon X.-D. Tan","doi":"10.1016/j.vlsi.2024.102202","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102202","url":null,"abstract":"<div><p>The Long-term reliability of a chip, encompassing factors like bias temperature instability (BTI), plays a substantial role in the chip's operational efficiency and overall lifespan. Most studies primarily center around performance-related aspects like delay and timing impacts, and fewer studies are performed on reliability impacts on the spatial power density and thermal profiles of the chips. In this study, we propose to investigate the BTI impacts on the spatial power density and temperature profiles of VLSI chips for the first time. We assessed the BTI aging impact on the on-chip spatial power density and temperature for two widely used circuit functional blocks (dual port RAM, Discrete Cosine Transform (DCT) block) at T = 130^<em>◦</em>C and T = 25^<em>◦</em>C to account for the worst-case BTI degradation, using degradation-aware cell libraries for a 10-year aging scenario. Furthermore, we showcased the essential role of BTI aging-aware timing analysis in evaluating the impact of BTI aging on total power, on-chip spatial power density, and thermal maps. Neglecting this aspect can result in a substantial underestimation of the results related to the parameters mentioned above. We developed a power map generation method from the circuit layout and power analysis from EDA tools. We demonstrate that both circuits’ maximum power density reduction is approximately 12 % and 20 %, respectively. Furthermore, to analyze the BTI impact on spatial temperature, we built the heat transfer model using a multiphysics tool to imitate a real chip (Intel i7-8650U) and performed thermal simulations to evaluate the spatial thermal map. The resulting maximum temperature reduction for both these circuits is approximately 10 % and 12 %, respectively, which is quite significant.</p><p>Our analysis has further unveiled that, in the context of a specific circuit, the position of maximum power density and the occurrence of a hot spot remains consistent over time, unaffected by aging. However, it's important to note that these positions can vary between different circuits, primarily influenced by the workload the circuit is currently handling. Furthermore, our findings demonstrate that the effects of Bias Temperature Instability (BTI) aging are significantly more pronounced when the circuit operates at higher temperatures (T = 130^<em>◦</em>C) compared to lower operating temperatures (T = 25^<em>◦</em>C).</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141097293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology","authors":"Qiyan Sun ,&nbsp;Ruiyong Tu ,&nbsp;Jin Xie ,&nbsp;Yihong Gong ,&nbsp;Sini Wu ,&nbsp;Jinghu Li ,&nbsp;Zhicong Luo","doi":"10.1016/j.vlsi.2024.102198","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102198","url":null,"abstract":"<div><p>Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>C</mi></mrow></msub></math></span>, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using <span><math><mrow><mn>0</mn><mo>.</mo><mn>18</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140816071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG","authors":"Mengdi Zhao,&nbsp;Hongjun Liu","doi":"10.1016/j.vlsi.2024.102200","DOIUrl":"10.1016/j.vlsi.2024.102200","url":null,"abstract":"<div><p>To address the limitations of existing chaotic maps, we proposed a non-degenerate <em>n</em>-dimensional (<em>n</em> ≥ 2) integer domain chaotic map (<em>n</em>D-IDCM) model that can construct any non-degenerate <em>n</em>-dimensional integer domain chaotic maps. Moreover, we analyzed its chaotic behavior through Lyapunov exponent, and found that the <em>n</em>D-IDCM generates chaotic sequences in the integer domain, which effectively resolves the issue of finite precision effect when implementing existing chaotic maps on computers or digital devices. To verify the effectiveness of <em>n</em>D-IDCM, we presented two instances to demonstrate how the positive Lyapunov exponents can be regulated by manipulating the parameter matrix. Subsequently, we have scrutinized their dynamical behavior using Kolmogorov entropy, sample entropy, correlation dimension and randomness testing via TestU01. Finally, to assess the feasibility of <em>n</em>D-IDCM, we devised a keyed pseudo random number generator (PRNG) based on a 3D-IDCM that can ensure superior randomness and unpredictability. Experimental results indicated that integer domain chaotic maps constructed using <em>n</em>D-IDCM have desirable Lyapunov exponents and exhibit ergodicity within a sufficient larger chaotic range.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140775056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}