Integration-The Vlsi Journal最新文献_第8页

A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting 采用新型开关驱动器增强技术的低压输入升压转换器，适用于室内太阳能收集

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-28 DOI: 10.1016/j.vlsi.2024.102214

Xiwen Zhu, Kaixuan Xu, Mingxue Li, Yufeng Zhang

{"title":"A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting","authors":"Xiwen Zhu, Kaixuan Xu, Mingxue Li, Yufeng Zhang","doi":"10.1016/j.vlsi.2024.102214","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102214","url":null,"abstract":"<div><p>In the indoor environment, the output voltage of a small photovoltaic cell is usually too low to charge the battery or utilize it directly. As a result, this paper proposed a low-voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting. The boost converter utilized switched-capacitor charge pump architecture. Compared with conventional charge pumps, the proposed boost converter uses driver enhancement technology, which improves the output current ability of the circuit and power conversion efficiency. Besides, an adaptive dead-time circuit is designed to further optimize conversion efficiency at low input voltage. The integrated circuit (IC) of the boost converter has been manufactured in a 180 nm BCD process and occupies an active chip area of 1.6mm × 0.6 mm. Experimental measurement results confirm that the voltage boost converter increased the input voltage by four times. And the lowest start-up voltage is 0.12 V. The voltage conversion efficiency is 98 % and the highest power conversion efficiency is 76.7 % at Vin of 0.5 V. The design is suitable for indoor solar energy harvesting.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"98 ","pages":"Article 102214"},"PeriodicalIF":1.9,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application 用于生物医学信号处理应用中快速傅立叶变换计算的混合 Radix-16 亭编码和基于舍入的近似 Karatsuba 乘法器

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-28 DOI: 10.1016/j.vlsi.2024.102215

Dinesh Kumar Jayaraman Rajanediran , Ganesh Babu C , Priyadharsini K , M. Ramkumar

{"title":"Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application","authors":"Dinesh Kumar Jayaraman Rajanediran , Ganesh Babu C , Priyadharsini K , M. Ramkumar","doi":"10.1016/j.vlsi.2024.102215","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102215","url":null,"abstract":"<div><p>Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. <strong>This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result.</strong> In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 <span><math><mrow><mi>μ</mi><msup><mi>m</mi><mn>2</mn></msup></mrow></math></span>, delay is 3.01 ns, power consumption is 0.021 mW and power delay product is 119 fJ.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"98 ","pages":"Article 102215"},"PeriodicalIF":1.9,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine 采用选择性充电和自适应放电方案的内容可寻址存储器，用于低功耗硬件搜索引擎

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-27 DOI: 10.1016/j.vlsi.2024.102213

Sheikh Wasmir Hussain , Telajala Venkata Mahendra , Sandeep Mishra , Anup Dandapat

{"title":"Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine","authors":"Sheikh Wasmir Hussain , Telajala Venkata Mahendra , Sandeep Mishra , Anup Dandapat","doi":"10.1016/j.vlsi.2024.102213","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102213","url":null,"abstract":"<div><p>Single clock cycle access feature of content-addressable memory (CAM) suits well for high-speed parallel content search operation in data-intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match-lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search-speed. A novel selective-charging and adaptive-discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full-swing CAM cell forms the basis of storage and comparison-evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 × 32-bit and 256 × 144-bit SCAD-CAM arrays dissipate only 0.45–0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low-power ML schemes, viz., low-swing precharge, division and control, and master–slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%–89.35% energy-delay. The average-power reduction of 1.8<span><math><mo>×</mo></math></span>–2.4<span><math><mo>×</mo></math></span> establishes the SCAD-CAM as a promising memory architecture for emerging search-intensive applications involving large-scale data workloads.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"98 ","pages":"Article 102213"},"PeriodicalIF":1.9,"publicationDate":"2024-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141323392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SET-detection low complexity burst error correction codes for SRAM protection 用于 SRAM 保护的 SET 检测低复杂度突发纠错码

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-25 DOI: 10.1016/j.vlsi.2024.102212

He Liu , Jiaqiang Li , Liyi Xiao , Tianqi Wang , Jie Li

引用次数: 0

Analysis of a new three-dimensional jerk chaotic system with transient chaos and its adaptive backstepping synchronous control 带有瞬态混沌的新型三维 Jerk 混沌系统及其自适应反步进同步控制分析

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-24 DOI: 10.1016/j.vlsi.2024.102210

Shaohui Yan , Jianjian Wang , Lin Li

{"title":"Analysis of a new three-dimensional jerk chaotic system with transient chaos and its adaptive backstepping synchronous control","authors":"Shaohui Yan , Jianjian Wang , Lin Li","doi":"10.1016/j.vlsi.2024.102210","DOIUrl":"10.1016/j.vlsi.2024.102210","url":null,"abstract":"<div><p>A new three-dimensional Jerk chaotic system with line equilibrium points is proposed. The system is researched in detail by the Lyapunov exponent graph, bifurcation diagram, phase diagram, and time domain waveform diagram, which show that the system has rich dynamical behaviors, such as eight types of coexisting attractors, extreme multistability of four different attractor states, and offset boosting in two directions. In addition, the system also has six types of transient chaos, which greatly increase the complexity of the system. We study the variation of the spectral entropy (SE) and C0 complexity when the system takes different initial values. Also, in this paper, the initial conditions under which the system is in a synchronized state are determined by initial values with higher complexity. The correctness of the theoretical analysis and numerical simulation is verified by circuit simulation and hardware experiments. Finally, the new system achieves synchronization control utilizing a designed adaptive backstepping controller, laying the foundation for its subsequent use in secure communications.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"98 ","pages":"Article 102210"},"PeriodicalIF":1.9,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141145038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL AiTO：利用 GNN 和 RL 同时优化栅极尺寸和缓冲器插入以实现时序优化

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-21 DOI: 10.1016/j.vlsi.2024.102211

Hongxi Wu , Zhipeng Huang , Xingquan Li , Wenxing Zhu

引用次数: 0

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation 温度系数为 8.83 ppm/°C、PSRR 为 75 dB、具有片式曲率补偿功能的亚阈值 CMOS 电压基准

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-20 DOI: 10.1016/j.vlsi.2024.102209

Tiedong Cheng, Hao Rao, Jinxiang Wei

{"title":"A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation","authors":"Tiedong Cheng, Hao Rao, Jinxiang Wei","doi":"10.1016/j.vlsi.2024.102209","DOIUrl":"https://doi.org/10.1016/j.vlsi.2024.102209","url":null,"abstract":"<div><p>A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the <span><math><mrow><mo>Δ</mo><msub><mi>V</mi><mrow><mi>G</mi><mi>S</mi></mrow></msub></mrow></math></span> of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"97 ","pages":"Article 102209"},"PeriodicalIF":1.9,"publicationDate":"2024-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141091016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection 在 fpga 上实现用于人类检测的猪特征提取的低资源消耗和高速硬件新方法

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-15 DOI: 10.1016/j.vlsi.2024.102208

Yuhai He , Jiye Huang , Yiming Pan

引用次数: 0

Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency 设计可合成的周期抖动传感器 IP，降低功耗并提高抗变化能力

IF 1.9 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-05-11 DOI: 10.1016/j.vlsi.2024.102207

Jinn-Shyan Wang , Yu-Hsuan Kuo

引用次数: 0

A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network 基于忆阻器-二极管交叉条和 CMOS 外围的逻辑器件，作为硬件神经网络的尖峰路由器