Path planning algorithm for data acquisition system based on 3D network-on-chip

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-07-18 DOI:10.1016/j.vlsi.2025.102484

Yunhui Deng , Chuanpei Xu

{"title":"Path planning algorithm for data acquisition system based on 3D network-on-chip","authors":"Yunhui Deng , Chuanpei Xu","doi":"10.1016/j.vlsi.2025.102484","DOIUrl":null,"url":null,"abstract":"<div><div>A data acquisition system model based on 3D Network-on-Chip (NoC) technology has been designed, with the system adopting the alternating sampling principle to achieve parallel data acquisition and transmission. In the NoC application system, a suitable routing strategy can effectively reduce network communication delay. The routing planning problem of a large number of functional nodes in the 3D NoC data acquisition system is addressed by a staged path planning algorithm (SPPA) proposed in this paper. In the first stage of the algorithm, the storage nodes with large data volumes in the data acquisition system ensure the high efficiency of data output through the established dedicated paths. In the subsequent stage, the collection nodes in the data collection system employ a global information-sharing mechanism through a parallel collaborative genetic algorithm to complete the globally optimal path planning while optimizing the global load balance. The experimental findings demonstrate that for data collection systems on-chip networks of varying sizes, the average network delay of the proposed algorithm is reduced by 14.63 %, 7.69 %, 16.27 %, and 13.38 %, respectively, compared with the XYZ routing algorithm. Furthermore, the proposed algorithm enhances the load balancing degree by 5.21 % on average in comparison with the genetic algorithm (GA).</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102484"},"PeriodicalIF":2.5000,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001415","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

A data acquisition system model based on 3D Network-on-Chip (NoC) technology has been designed, with the system adopting the alternating sampling principle to achieve parallel data acquisition and transmission. In the NoC application system, a suitable routing strategy can effectively reduce network communication delay. The routing planning problem of a large number of functional nodes in the 3D NoC data acquisition system is addressed by a staged path planning algorithm (SPPA) proposed in this paper. In the first stage of the algorithm, the storage nodes with large data volumes in the data acquisition system ensure the high efficiency of data output through the established dedicated paths. In the subsequent stage, the collection nodes in the data collection system employ a global information-sharing mechanism through a parallel collaborative genetic algorithm to complete the globally optimal path planning while optimizing the global load balance. The experimental findings demonstrate that for data collection systems on-chip networks of varying sizes, the average network delay of the proposed algorithm is reduced by 14.63 %, 7.69 %, 16.27 %, and 13.38 %, respectively, compared with the XYZ routing algorithm. Furthermore, the proposed algorithm enhances the load balancing degree by 5.21 % on average in comparison with the genetic algorithm (GA).

查看原文本刊更多论文

基于三维片上网络的数据采集系统路径规划算法

设计了一种基于三维片上网络（NoC）技术的数据采集系统模型，该系统采用交替采样原理实现数据的并行采集和传输。在NoC应用系统中，合适的路由策略可以有效降低网络通信时延。本文提出了一种分段路径规划算法（SPPA），解决了三维NoC数据采集系统中大量功能节点的路由规划问题。在算法的第一阶段，数据采集系统中数据量较大的存储节点通过建立的专用路径保证数据输出的高效率。后续阶段，数据采集系统中的采集节点通过并行协同遗传算法实现全局信息共享机制，在优化全局负载均衡的同时完成全局最优路径规划。实验结果表明，对于不同规模的数据采集系统片上网络，与XYZ路由算法相比，该算法的平均网络时延分别降低了14.63%、7.69%、16.27%和13.38%。与遗传算法（GA）相比，该算法的负载均衡度平均提高了5.21%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.