A hybrid entropy source scheme for true random number generator

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-07-07 DOI:10.1016/j.vlsi.2025.102473

Zhaoxiong Guan, Mingxin Liu, Jinqiang Xu, Cong Lin

引用次数: 0

Abstract

True random number generators (TRNGs) are gaining increasing attention as essential components in information security systems. In this paper, a dual-path reconfigurable ring (DPRR) that generates both jitter and metastability is proposed. Its fundamental unit consists of seven XOR gates and two 2-to-1 multiplexers (MUXs). The advantage of this method lies in utilizing the ability of XOR gates to quickly accumulate jitter and the characteristic of the 2-to-1 MUX to switch the loop path, simultaneously inducing jitter and instability in the proposed scheme. The DPRR-based TRNG was deployed on the Field Programmable Gate Array (FPGA) platforms with Artix-7 and Kintex-7 using automatic layout and routing mode, which consumed 33 Look-up Tables (LUTs) and 12 D Flip-Flops (DFFs) to achieve 200/300 Mbps throughput. Experimental results demonstrate that the random sequences generated by this TRNG pass the NIST SP800-22, NIST SP800-90B, AIS-31, and robustness test without requiring post-processing circuits.

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真随机数生成器的混合熵源方案

真随机数发生器（trng）作为信息安全系统的重要组成部分，越来越受到人们的关注。本文提出了一种同时产生抖动和亚稳的双路可重构环（DPRR）。它的基本单元由七个异或门和两个2对1多路复用器（MUXs）组成。该方法的优点在于利用异或门快速积累抖动的能力和2对1 MUX的特性来切换环路路径，同时在所提出的方案中引起抖动和不稳定。基于dprr的TRNG与Artix-7和Kintex-7一起部署在现场可编程门阵列（FPGA）平台上，采用自动布局和路由模式，消耗33个查找表（lut）和12个D触发器（dff）来实现200/300 Mbps的吞吐量。实验结果表明，该TRNG生成的随机序列在不需要后处理电路的情况下，通过了NIST SP800-22、NIST SP800-90B、AIS-31和鲁棒性测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.