A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Guru Siva Subramanian V., Deepika Sree T.N. , Aditya S.
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引用次数: 0

Abstract

The essentiality of efficient hardware multipliers has increased as they have a huge impact on the performance and the power consumption of digital systems. This work proposes a novel 8-bit unsigned multiplier architecture which combines the Modified Russian Peasant algorithm with a Kogge-Stone adder. The aim of the proposed design is to minimize resource usage and power consumption while retaining high speed and accuracy. The effective optimization of the multiplier design led to a significant reduction in area utilization and overall power consumption, making it highly suitable for implementing in resource constrained systems. The design is validated using Xilinx Vivado tool and is implemented on Nexys A7 FPGA board. The results show that the proposed multiplier utilizes fewer devices (50%–70% less) and has comparative speed and power consumption with respect to the conventional multipliers. The proposed multiplier design can be used for biomedical systems such as wearable health monitors and implantable medical devices, where compact size and energy efficiency are key considerations. This efficient multiplier architecture ensures prolonged battery life and reliable performance, enabling advanced signal processing tasks such as signal filtering, enhancement of medical imaging and noise reduction in hearing aids. These features emphasize the multiplier’s potential to enable substantial enhancements in high-performance, area-sensitive, and power-sensitive biomedical applications, which will contribute to the forthcoming compact and energy-efficient healthcare systems.
用于生物医学应用的低成本区域效率改良俄罗斯农民倍增器(MRPM)
高效硬件乘数器的重要性已经增加,因为它们对数字系统的性能和功耗有巨大的影响。本文提出了一种新的8位无符号乘法器架构,该架构将改进的俄罗斯农民算法与Kogge-Stone加法器相结合。所提出的设计的目的是尽量减少资源使用和功耗,同时保持高速度和准确性。乘数设计的有效优化导致了面积利用率和总体功耗的显著降低,使其非常适合在资源受限的系统中实施。该设计通过Xilinx Vivado工具进行验证,并在Nexys A7 FPGA板上实现。结果表明,与传统乘法器相比,所提出的乘法器使用更少的器件(减少50%-70%),并且具有相对的速度和功耗。提出的倍增器设计可用于生物医学系统,如可穿戴健康监视器和植入式医疗设备,其中紧凑的尺寸和能源效率是关键考虑因素。这种高效的倍增器架构可确保延长电池寿命和可靠的性能,从而实现先进的信号处理任务,如信号滤波、增强医疗成像和助听器降噪。这些特性强调了乘法器在高性能、面积敏感和功率敏感的生物医学应用方面的潜力,这将有助于即将到来的紧凑和节能的医疗保健系统。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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