Integration-The Vlsi Journal最新文献

{"title":"Dynamics and circuit implementation of a novel coupled discrete memristive system","authors":"Kotadai Zourmba ,&nbsp;Beining Fu ,&nbsp;Kehui Sun","doi":"10.1016/j.vlsi.2025.102504","DOIUrl":"10.1016/j.vlsi.2025.102504","url":null,"abstract":"<div><div>This paper presents the design and analysis of a 3D memristor-based discrete chaotic system, combining theoretical exploration with practical implementation. The proposed system is derived from a sine discrete memristor model and exhibits rich hyperchaotic dynamics, as demonstrated through stability analysis, bifurcation diagrams, Lyapunov exponents, and complexity measures (spectral entropy <span><math><mrow><mi>S</mi><mi>E</mi></mrow></math></span> and <span><math><msub><mrow><mi>C</mi></mrow><mrow><mn>0</mn></mrow></msub></math></span> complexity). Numerical simulations reveal broad chaotic regions and extreme sensitivity to parameter variations, including hyperchaos with multiple positive Lyapunov exponents. A digital and analog realization is achieved via a PSim-simulated circuit employing sample-and-hold modules, operational amplifiers, and nonlinear components, with results closely matching numerical predictions. Furthermore, the system is leveraged to construct a pseudo-random number generator (PRNG), which successfully passes all NIST SP800-22 randomness tests, validating its potential for secure communication and encryption applications. The study bridges theoretical chaos analysis with tangible electronic implementation, offering insights into memristive discrete systems for high-performance chaos-based technologies.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102504"},"PeriodicalIF":2.5,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144827046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient processor verification by tautologies-derived universal properties model checking","authors":"Yufeng Li ,&nbsp;Yiwei Ci ,&nbsp;Qiusong Yang ,&nbsp;Enyuan Tian","doi":"10.1016/j.vlsi.2025.102502","DOIUrl":"10.1016/j.vlsi.2025.102502","url":null,"abstract":"<div><div>Verification is a critical and challenging task in processor development, and there is an objective need for more efficient verification methods. Model checking, with its ability to detect corner cases, has become a key approach to ensuring the correctness of designs. However, the process of constructing properties is highly dependent on expert knowledge, time-consuming, and prone to errors.</div><div>The groundbreaking <em>Symbolic Quick Error Detection (SQED)</em> introduces a <em>self-consistency universal property</em> that is microarchitecture-independent, thereby circumventing the laborious process of manual property construction. However, the verification of the self-consistency property, which checks whether the results of original and duplicate instructions performing the same function are consistent, presents two significant issues. First, bugs affecting both the original and duplicate instructions simultaneously can lead to false positives (property verification passes, but the design contains bugs) in the verification results. Second, the system variables affected by the self-consistency are numerous, and the process of unfolding the transition system copies a large number of variables, which can easily lead to computation explosion. To address these issues, this paper proposes a tautologies-derived universal properties model checking. Our method verifies a set of tautology universal properties that cover both the data paths and control flow of the processor, thereby avoiding the false positive issues inherent in the single self-consistency property. Furthermore, a single tautology covering the data path is simpler than self-consistency, reducing the computational overhead for solvers when checking individual properties, which facilitates the detection of difficult bugs. We compare four methods based on universal properties in our experimental results, demonstrating the effectiveness of our approach.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102502"},"PeriodicalIF":2.5,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144830010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fast transient response capless low-dropout regulator with NMOS-FVF structure","authors":"Jiahao Xiong,&nbsp;Xiao Zhao,&nbsp;Bojiang Zhang,&nbsp;Yicheng Peng","doi":"10.1016/j.vlsi.2025.102481","DOIUrl":"10.1016/j.vlsi.2025.102481","url":null,"abstract":"<div><div>This paper presents an NMOS-FVF low-dropout regulator (LDO) with adaptive biasing. Leveraging the small gate capacitance and adaptive biasing mechanism, the proposed LDO achieves minimal undershoot and overshoot, along with an exceptionally short recovery time. Additionally, strategic incorporation of adaptive biasing substantially enhances load regulation, effectively addressing the limitations of inadequate load regulation commonly observed in traditional FVF-LDOs. The proposed design was fabricated in a 180 nm CMOS process, featuring a quiescent current of 110 <span><math><mi>μ</mi></math></span>A and a maximum load current of 50 mA. Transient simulation results demonstrate an undershoot of 64 mV, an overshoot of 42 mV, and a recovery time of 30 ns.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102481"},"PeriodicalIF":2.5,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144781748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An attractor-controllable memristive Hopfield neural network and its application on voice encryption","authors":"Zhenyao Li ,&nbsp;Jie Jin ,&nbsp;Daobing Zhang ,&nbsp;Chaoyang Chen","doi":"10.1016/j.vlsi.2025.102500","DOIUrl":"10.1016/j.vlsi.2025.102500","url":null,"abstract":"<div><div>Due to the unpredictability, sensitivity, and complexity of chaotic sequences, they have become special tools in various security applications. Previous studies have primarily focused on general multi-scroll attractor chaotic systems, while research on symmetric attractor-controllable multi-scroll chaotic systems remains relatively limited. Symmetric attractor-controllable multi-scroll chaotic systems typically exhibit more flexible and diverse evolutionary characteristics and higher stability, potentially leading to more stable system responses. Therefore, an attractor-controllable memristive Hopfield neural network (AMHNN) model is proposed in this work. By implementing multilevel logic pulse modulation of memristor synaptic coupling, the proposed AMHNN model enables the controllable generation of symmetric vortex-like double-scroll attractors. Dynamic analysis demonstrates that the AMHNN model can produce 1 to 18 symmetric double-scroll attractors under parameter modulation, with their quantity determined by memristor parameters and pulse stages. When the coupling strength <span><math><mrow><msub><mrow><mi>k</mi></mrow><mrow><mn>1</mn></mrow></msub><mo>&gt;</mo><mn>0</mn><mo>.</mo><mn>7</mn></mrow></math></span>, the system continuously transitions between chaotic and periodic behaviors through bifurcation, and the maximum Lyapunov exponent remains positive, verifying the stability of chaotic characteristics. Hardware implementation based on Xilinx ZYNQ-7000 series FPGA shows that the oscilloscope-measured phase diagrams highly align with the simulation results, confirming the reliability of theoretical analyses. This research provides a solution for chaotic encryption that balances dynamical complexity and engineering feasibility, and its controllable attractor characteristics demonstrate application potential in scenarios such as voice encryption.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102500"},"PeriodicalIF":2.5,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144781749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semi-adaptive distributed approach for triplet-based architecture inter-core communication Network-on-Chip","authors":"Karim Soliman,&nbsp;Chunfeng Li,&nbsp;Shi Feng","doi":"10.1016/j.vlsi.2025.102489","DOIUrl":"10.1016/j.vlsi.2025.102489","url":null,"abstract":"<div><div>Network-on-Chip (NoC) architectures offer significant performance improvements over traditional bus-based systems. However, as NoC designs become more complex, congestion within channels and buffers can degrade performance. Efficient routing algorithms are essential to mitigate congestion and optimize overall NoC performance. This study examines Triplet-Based Architecture (TriBA) architecture and its baseline deterministic shortest-path routing algorithm. The deterministic nature of this algorithm, combined with TriBA’s inherent characteristics, may exacerbate congestion and lead to routing deadlocks, particularly in high-traffic nodes. This work introduces a novel two-stage semi-adaptive routing algorithm to address congestion within TriBA-NoC. The proposed approach leverages congestion levels within downstream buffers of TriBA sub-level apex vertices as an additional routing metric solely at the source node. The primary goal of the proposed strategy is to alleviate congestion, specifically at hot nodes, which in turn leads to reduced communication latency, shorter queuing times in downstream buffers, lower power consumption, and an enhancement in overall network throughput. Comprehensive simulations utilizing gem5-HeteroGarnet have substantiated the effectiveness of the proposed semi-adaptive routing for TriBA-NoC. The approach yields a significant decrease in latency (up to 31.71%), and a decline in buffer queuing time, with reductions reaching 43.14%. Additionally, it enhances throughput by 6.28% and lowers downstream buffer power consumption by an average of 12.15% across various traffic patterns when compared to baseline algorithms. These improvements are evident in practical workloads, as demonstrated by simulations using the PARSEC benchmark suite, which reveal latency reductions between 0.91% and 45.86%. Nonetheless, these performance enhancements are accompanied by a modest power overhead, estimated at approximately 3.94%.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102489"},"PeriodicalIF":2.5,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144772418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heterogeneous neural network based on locally active memristor with multiple firing patterns","authors":"Ke Meng,&nbsp;Yinghong Cao,&nbsp;Xianying Xu,&nbsp;Jun Mou","doi":"10.1016/j.vlsi.2025.102490","DOIUrl":"10.1016/j.vlsi.2025.102490","url":null,"abstract":"<div><div>With the development of information technology and neurobiology, there is an urgent need for a memory element with bionic properties to simulate the interactions among neurons. On this basis, a novel locally active memristor (LAM) model is designed, of which the memory properties are utilized to construct a coupled system of three-dimensional Hopfield neural network (HNN) and Hindmarsh–Rose (HR) neurons to simulate neuronal activities. First, the nonvolatility and local activity of the memristor is verified by the power-off plot (POP) and its direct current (DC) <span><math><mi>V</mi></math></span> - <span><math><mi>I</mi></math></span> plot. The device exhibits typical bistable resistance-switching behavior, maintaining two stable resistance states upon power-off, which confirms its non-volatile memory characteristics. A significant negative differential resistance (NDR) region observed in DC <span><math><mi>V</mi></math></span> - <span><math><mi>I</mi></math></span> curves directly verifies its local activity, indicating potential for active signal processing. Second, the complex dynamical behavior of HNN-HR is probed by numerical simulation, adjusting the coupling strength, synaptic weights and HR neuron parameters to demonstrate the bionic properties. The research results show that not only are multiple hidden attractor structures exhibited by the model, but also typical nonlinear phenomena such as transient chaos and intermittent chaos can be reproduced by it, and the dynamic transition between different chaotic firing modes can be realized. In addition, the phenomena of multi- state coexisting attractors and the expansion and migration of attractor topological structures are observed in the model. Finally, by means of the TMS320F28335 digital signal processing (DSP) platform, through the system architecture featuring the MAX3232 communication interface for interaction with the computer and the DAC8552 D/A converter for output to the oscilloscope, the generation of attractors of the HNN-HR model is achieved, and the feasibility of its application in digital circuits is verified. The construction of neural networks by simulating biological synapses through memristors offers a promising avenue for exploring brain function and its bionics.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102490"},"PeriodicalIF":2.5,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144772419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of 2.54 GHz active inductor-based LC-voltage controlled oscillator for bluetooth/WLAN applications","authors":"Kusuma Neerugatti,&nbsp;Venugopal Pakala","doi":"10.1016/j.vlsi.2025.102487","DOIUrl":"10.1016/j.vlsi.2025.102487","url":null,"abstract":"<div><div>The paper presents a 2.54 GHz Active Inductor-based LC-Voltage Controlled Oscillator (AI-based LC-VCO) design. The AI is constructed based on a single-ended common-source NMOS/PMOS cascade model that generates negative transconductance in the gyrator model. The proposed design is a combination of AI, NMOS cross-coupled pair, and fixed tail current biasing together that optimizes the Q-point to maintain output swing, reduces power consumption and lowers phase noise at a wide tuning range. The findings demonstrate the active VCOs post-layout performance with phase noise of −117.61 dBc/1 MHz offset, power of 0.122 mW, FTR of 102.20 %, and occupies a layout area of 0.09177 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> with tape-out. Also, advanced simulations under Monte-Carlo and PVT analysis at Military standards (Temp. <span><math><mrow><mo>°</mo><mi>C</mi></mrow></math></span>: −55, 27, 85) are performed using the Cadence UMC-180 nm process at a supply of 1.8 V. Ultimately, it finds a high FoM of −141.15 dBc/Hz compared to current AI-based LC-VCOs. Therefore, the work is suitable for designing sub-6 GHz Charge Pump-PLLs for modern 5G and 6G Bluetooth/WLAN applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102487"},"PeriodicalIF":2.5,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144766869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust analog/RF circuit design via Cycle-Consistent Generative Adversarial Networks","authors":"Nanlin Guo ,&nbsp;Jun Tao ,&nbsp;Xuan Zeng ,&nbsp;Xin Li","doi":"10.1016/j.vlsi.2025.102488","DOIUrl":"10.1016/j.vlsi.2025.102488","url":null,"abstract":"<div><div>In this paper, we propose a novel method based on Cycle-Consistent Generative Adversarial Networks (Cycle-GAN) to efficiently synthesize robust analog/RF circuits. The key idea is to learn a mathematical mapping between nominal and robust designs by using a Cycle-GAN, which can be used to convert a given nominal design to its robust version with great computational efficiency. The proposed Cycle-GAN is learned from a large number of nominal designs synthesized by EDA tools and a small number of robust circuits manually designed by human experts. Hence, it is expected to appropriately incorporate the human design knowledge that is often difficult to capture by other state-of-the-art methods. Two circuit examples demonstrate that the proposed approach can accurately synthesize robust analog/RF circuits with low computational cost.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102488"},"PeriodicalIF":2.5,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144722288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography","authors":"Ahmed Alotaibi,&nbsp;Mohammed Benaissa","doi":"10.1016/j.vlsi.2025.102479","DOIUrl":"10.1016/j.vlsi.2025.102479","url":null,"abstract":"<div><div>The demand for efficient polynomial multiplication in post-quantum cryptosystems calls for the exploration of alternative methods to the fast number-theoretic transform framework. This paper presents a parametric, scalable, and efficient hardware architecture for polynomial multiplication in lattice-based cryptography. The proposed design adopts the schoolbook method to enable design space exploration for post-quantum cryptographic applications. Central to this approach and responsible for the core computation, the Multiply-and-Accumulate (MAC) unit is optimised through a single-stage pipelined design that employs truncated coefficient-wise multiplication to maximise hardware efficiency in terms of area and execution time. The implementation results demonstrate marked improvements, achieving execution time reductions ranging from 36.34% to 50.94% compared to previous works when the modulus <span><math><mi>q</mi></math></span> is a power of two.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102479"},"PeriodicalIF":2.2,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144716116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamical analysis, hardware implementation, and image encryption application of new 4D discrete hyperchaotic maps based on parallel and cascade memristors","authors":"Fei Yu ,&nbsp;Xuqi Wang ,&nbsp;Rongyao Guo ,&nbsp;Zhijie Ying ,&nbsp;Shuo Cai ,&nbsp;Jie Jin","doi":"10.1016/j.vlsi.2025.102475","DOIUrl":"10.1016/j.vlsi.2025.102475","url":null,"abstract":"<div><div>In this paper, the construction of a series of 4D discrete hyperchaotic maps is achieved through employing parallel and cascade operations on discrete memristors (DMs). Initially, DMs are integrated in both parallel and cascade configurations to form parallel DMs and cascade DMs, respectively. Subsequently, the nonlinear terms derived from these parallel and cascade DMs are coupled into the sine map and logistic map, generating four 4D discrete hyperchaotic maps that exhibit diverse dynamical behaviors. The dynamical properties of the proposed maps are systematically investigated through the analysis of dynamical behaviors and the distribution of the first Lyapunov exponent (LE). The dynamical phenomena of the hyperchaotic maps are further elucidated by examining the initial-value-dependent LE spectrum, bifurcation diagrams, and the mean values of state variables. Notably, the observed dynamical phenomena encompass four types of rare hyperchaotic behaviors, discharge pattern transitions, and coexistence phenomena. Moreover, the spectral entropy complexity is calculated across various parameter planes, revealing a high degree of complexity in the proposed system. The hyperchaotic map is implemented on Field-Programmable Gate Array (FPGA) hardware implementation platform, demonstrating its practical feasibility. Furthermore, an efficient image encryption scheme is designed, and its robust security performance is validated through comprehensive security analyses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"104 ","pages":"Article 102475"},"PeriodicalIF":2.2,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}