Integration-The Vlsi Journal最新文献_第7页

DAGNN-RE: Directed acyclic graph neural network for functional reverse engineering of gate-level netlist

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-30 DOI: 10.1016/j.vlsi.2024.102343

Zongtai Li, Liang Yang, Mian Lou

{"title":"DAGNN-RE: Directed acyclic graph neural network for functional reverse engineering of gate-level netlist","authors":"Zongtai Li, Liang Yang, Mian Lou","doi":"10.1016/j.vlsi.2024.102343","DOIUrl":"10.1016/j.vlsi.2024.102343","url":null,"abstract":"<div><div>Functional reverse engineering of gate-level netlist is a crucial means for detecting the functionality of third-party IPs and enhancing IC security. The state-of-the-art method GNN-RE accurately identifies sub-circuits in flattened netlists but struggles to generalize effectively to unseen functionally-equivalent structurally-different netlists because it only extracts the structural features of the netlist. This work introduces an innovative GNN-based approach DAGNN-RE, that can accurately identify sub-circuits in combinational netlists and exhibits superior generalization capabilities for functionally-equivalent structurally-different netlists. The improved performance rests on learning both the structural and functional attributes of netlist instead of merely increasing the amount of training data. Specifically, for structural attributes, DAGNN-RE employs the partial order in message passing of Directed Acyclic Graph Neural Network (DAGNN) to extract the inherent DAG nature of netlist structure. For functional attributes, DAGNN-RE integrates the boolean function of logic gates and the time series update function following the propagation of the circuit signals to extract functionality at the sub-circuit level. Furthermore, the signal probability of logic gates is incorporated to boost the capture of functional attributes. We constructed four extra custom datasets based on the GNN-RE open-sourced dataset to test the accuracy, scalability, and generalization ability. The experimental results show that DAGNN-RE outperforms GNN-RE across all five datasets, suggesting that our approach offers more practical than GNNRE. We derived another five custom datasets from GNN-RE open-source RTL to validate the application in equivalent timing scenarios. The experimental results show that DAGNN-RE still outperforms GNN-RE, demonstrating that our approach maintains a significant advantage even for netlists that are timing and functionally equivalent but structurally different.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102343"},"PeriodicalIF":2.2,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-30 DOI: 10.1016/j.vlsi.2024.102337

Youngwoo Jeong, Joungmin Park, Raehyeong Kim, Seung Eun Lee

{"title":"SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources","authors":"Youngwoo Jeong, Joungmin Park, Raehyeong Kim, Seung Eun Lee","doi":"10.1016/j.vlsi.2024.102337","DOIUrl":"10.1016/j.vlsi.2024.102337","url":null,"abstract":"<div><div>Approximate computing constitutes a paradigm in which accuracy is exchanged for enhanced energy efficiency when contrasted with conventional computing methodologies. This approach has been devised to address the escalating demand stemming from the rapid expansion of application systems. This paper proposes an approximate multiplier for systems with heavy computational load. By amalgamating the attributes of a Dynamic range unbiased multiplier (DRUM) with an Approximate wallace tree multiplier (AWTM), we have devised a Synergetic energy-efficient approximate multiplier (SEAM) aimed at mitigating the occurrence of worst-case errors inherent in AWTM. The SEAM was analyzed for circuit area and power consumption using Design Compiler with Synopsys GPDK 32 nm. Experimental results demonstrated that SEAM achieved up to 80.46% reduction in circuit area and 82.6% reduction in power consumption compared to a precise multiplier. Furthermore, compared to DRUM, SEAM showed a 15.55% reduction in circuit area and 45.73% reduction in power consumption. In order to validate the feasibility of the proposed approximate multiplier, the circuit was implemented on a Field-programmable gate array (FPGA) and applied to a fuzzy logic-based pathfinding algorithm and a Convolutional neural network (CNN) accelerator. For the pathfinding algorithm, most error metrics of the SEAM showed similar values to the DRUM. Moreover, when applied to the CNN accelerator and experimented with the CIFAR-10 dataset and MNIST dataset, the proposed multiplier exhibited identical precision, recall, and F1 score values. Despite applying SEAM, we achieved a maximum 3.1% increase in classification metrics for a specific case. These results indicate the significant potential of the SEAM in reducing the area of overall system while minimizing errors.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102337"},"PeriodicalIF":2.2,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Image encryption algorithm based on the dynamic RNA computing and a new chaotic map

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-18 DOI: 10.1016/j.vlsi.2024.102336

Shuang Zhou , Yi Wei , Yingqian Zhang , Herbert Ho-Ching Iu , Hao Zhang

引用次数: 0

Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102335

Lin Yang , Jiarong Wu , Hailong Ma

{"title":"Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter","authors":"Lin Yang , Jiarong Wu , Hailong Ma","doi":"10.1016/j.vlsi.2024.102335","DOIUrl":"10.1016/j.vlsi.2024.102335","url":null,"abstract":"<div><div>Single-inductor dual-output (SIDO) boost converters have been applied in portable electronic devices, but the cross-regulation severely deteriorates its dynamic performance. Meanwhile, parasitic parameters have a significant impact on the cross-regulation. To suppress the cross-regulation and improve the performance of a non-ideal SIDO boost converter, an improved adaptive sliding mode control strategy is proposed in this paper. Considering the parasitic resistor of the inductor, capacitors and MOSFETs, a nonlinear mathematical model of the non-ideal SIDO boost converter is established. Based on the differential geometry theory, a set of output functions that meet the requirements of exact feedback linearization is constructed to linearize the model. An improved adaptive reaching law is proposed to reduce the sliding mode chattering. Combining adaptive technology, improved adaptive sliding mode controllers are designed. The stability and robustness of the control system are verified based on Lyapunov theory. Compared with the existing control method, simulation and experimental results show that the proposed control strategy provides a rapider response, lower cross-regulation, and better performance.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102335"},"PeriodicalIF":2.2,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-performance CORDIC-based approximate MAC architectures for FPGA platforms

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102338

Burhan Khurshid

{"title":"High-performance CORDIC-based approximate MAC architectures for FPGA platforms","authors":"Burhan Khurshid","doi":"10.1016/j.vlsi.2024.102338","DOIUrl":"10.1016/j.vlsi.2024.102338","url":null,"abstract":"<div><div>CORDIC is a versatile algorithm frequently used in different signal-processing operations. While using CORDIC-based computations in evaluating trigonometric and transcendental functions is quite prevalent, the resource overhead associated with its implementation does not justify its use in evaluating linear functions like multiplication and addition. However, with the emergence of approximate computing as an attractive paradigm for error-resilient applications, the algorithm can be used to design approximate linear computational units that completely justify the accuracy-performance trade-offs. In this paper, we model the CORDIC-based computations to emulate the multiply-accumulate operation, albeit with some loss of accuracy. We specifically present two incremental CORDIC-based multiply-accumulate architectures with an attempt to improve the accuracy-performance trade-offs with each increment. A detailed Pareto analysis for 8 and 16-bit unsigned and signed multiply-accumulate structures is conducted to determine the optimum number of computing stages and the associated bit-precision of the intermediate results. Accuracy and performance analysis using 6th and 7th generation FPGAs reveals a substantial improvement over state-of-the-art designs. The proposed architectures are also tested using three image processing applications, and the output results are promising.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102338"},"PeriodicalIF":2.2,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localisation of malicious nets in integrated circuits using unsupervised methodologies

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-16 DOI: 10.1016/j.vlsi.2024.102312

Tapobrata Dhar, Chandan Giri, Surajit Kumar Roy

引用次数: 0

ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-14 DOI: 10.1016/j.vlsi.2024.102315

Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi

引用次数: 0

CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-13 DOI: 10.1016/j.vlsi.2024.102333

Salih Yalcin , Hamdi Burak Usul , Gulay Yalcin

{"title":"CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression","authors":"Salih Yalcin , Hamdi Burak Usul , Gulay Yalcin","doi":"10.1016/j.vlsi.2024.102333","DOIUrl":"10.1016/j.vlsi.2024.102333","url":null,"abstract":"<div><div>Traveling Salesman Problem (TSP) is one of the significant problems in computer science which tries to find the shortest path for a salesman who needs to visit a set of cities and it is involved in many computing problems such as networks, genome analysis, logistics etc. Using parallel executing paradigms, especially GPUs, is appealing in order to reduce the problem solving time of TSP. One of the main issues in GPUs is to have limited GPU memory which would not be enough for the entire data. Therefore, transferring data from the host device would reduce the performance in execution time. In this study, we applied three data compression methodologies to represent cities in the TSP such as (1) Using Greatest Common Divisor (2) Shift Cities to the Origin (3) Splitting Surface to Grids. Therefore, we include more cities in GPU memory and reduce the number of data transfers from the host device. We implement our methodology in Iterated Local Search (ILS) algorithm with 2-opt and The Lin–Kernighan–Helsgaun (LKH) Algorithm. We show that our implementation presents more than 25% performance improvement for both algorithms.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102333"},"PeriodicalIF":2.2,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143146485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102320

Christoph Hazott, Florian Stögmüller, Daniel Große

{"title":"Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries","authors":"Christoph Hazott, Florian Stögmüller, Daniel Große","doi":"10.1016/j.vlsi.2024.102320","DOIUrl":"10.1016/j.vlsi.2024.102320","url":null,"abstract":"<div><div>Embedded graphics libraries are part of the <em>Firmware</em> (FW) of embedded systems and provide complex functionalities optimized for specific hardware. After unit testing of embedded graphics libraries, integration testing is a significant challenge, in particular since the hardware is needed to obtain the output image as well as the inherent difficulty in defining the reference result. In this paper, we present a novel approach focusing on integration testing of embedded graphic libraries. We leverage <em>Virtual Prototypes</em> (VPs) and integrate them with <em>Metamorphic Testing</em> (MT). <em>Metamorphic Testing</em> (MT) is a software testing technique that uncovers faults or issues in a system by exploring how its outputs change under predefined input transformations, without relying on explicit oracles or predetermined results. In combination with virtualizing the displays in VPs, we even eliminate the need for physical hardware. This allows us to develop a <em>Metamorphic Testing</em> (MT) framework automating the verification process. In our evaluation, we demonstrate the effectiveness of our <em>Metamorphic Testing</em> (MT) framework. On an extended RISC-V <em>Virtual Prototype</em> (VP) for the GD32VF103VBT6 platform, we found 15 distinct bugs for the widely used TFT_eSPI embedded graphics library, confirming the strength our approach. We finish the evaluation of our <em>Metamorphic Testing</em> (MT) approach by discussing the achieved structural coverage for function, line and branch coverage.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102320"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS

IF 2.2 3区工程技术

Integration-The Vlsi Journal Pub Date : 2024-12-10 DOI: 10.1016/j.vlsi.2024.102310

Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.

{"title":"Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS","authors":"Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.","doi":"10.1016/j.vlsi.2024.102310","DOIUrl":"10.1016/j.vlsi.2024.102310","url":null,"abstract":"<div><div>Intrusion Detection System (IDS) is a type of packet filtering that ensures network security by analyzing the packets flowing through the network and detecting any malicious pattern(s) present in them. In signature-based NIDS, pattern matching is the critical step as it determines the system’s performance. The throughput of the system, inherently, relies on the delay required to match an input pattern. Hardware-based high-speed pattern matching algorithms are popularly used to speed up the pattern matching process and improve the system’s performance. Ternary Content Addressable Memory (TCAM) is one such memory in which the input pattern is simultaneously launched on all the match lines. Since all the match lines and search lines are activated at a given instance, the power consumed per search is extremely high. To address this issue, this paper proposes an approach in which the match is carried out with an n-bit prefix of the input pattern that enables a smaller TCAM unit, which contains the patterns having this prefix. A significant improvement in energy is observed since a single TCAM segment is enabled for a single search. The results are compared with existing solutions, and energy improvement of 96.1% is observed with worst case and best case throughput of <span><math><mrow><mn>17</mn><mi>G</mi><mi>b</mi><mi>p</mi><mi>s</mi></mrow></math></span> and <span><math><mrow><mn>148</mn><mi>G</mi><mi>b</mi><mi>p</mi><mi>s</mi></mrow></math></span>, respectively.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102310"},"PeriodicalIF":2.2,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0