A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography

The demand for efficient polynomial multiplication in post-quantum cryptosystems calls for the exploration of alternative methods to the fast number-theoretic transform framework. This paper presents a parametric, scalable, and efficient hardware architecture for polynomial multiplication in lattice-based cryptography. The proposed design adopts the schoolbook method to enable design space exploration for post-quantum cryptographic applications. Central to this approach and responsible for the core computation, the Multiply-and-Accumulate (MAC) unit is optimised through a single-stage pipelined design that employs truncated coefficient-wise multiplication to maximise hardware efficiency in terms of area and execution time. The implementation results demonstrate marked improvements, achieving execution time reductions ranging from 36.34% to 50.94% compared to previous works when the modulus $q$ is a power of two.