Efficient processor verification by tautologies-derived universal properties model checking

Verification is a critical and challenging task in processor development, and there is an objective need for more efficient verification methods. Model checking, with its ability to detect corner cases, has become a key approach to ensuring the correctness of designs. However, the process of constructing properties is highly dependent on expert knowledge, time-consuming, and prone to errors.

The groundbreaking Symbolic Quick Error Detection (SQED) introduces a self-consistency universal property that is microarchitecture-independent, thereby circumventing the laborious process of manual property construction. However, the verification of the self-consistency property, which checks whether the results of original and duplicate instructions performing the same function are consistent, presents two significant issues. First, bugs affecting both the original and duplicate instructions simultaneously can lead to false positives (property verification passes, but the design contains bugs) in the verification results. Second, the system variables affected by the self-consistency are numerous, and the process of unfolding the transition system copies a large number of variables, which can easily lead to computation explosion. To address these issues, this paper proposes a tautologies-derived universal properties model checking. Our method verifies a set of tautology universal properties that cover both the data paths and control flow of the processor, thereby avoiding the false positive issues inherent in the single self-consistency property. Furthermore, a single tautology covering the data path is simpler than self-consistency, reducing the computational overhead for solvers when checking individual properties, which facilitates the detection of difficult bugs. We compare four methods based on universal properties in our experimental results, demonstrating the effectiveness of our approach.