{"title":"用于蓝牙/WLAN应用的2.54 GHz有源电感lc压控振荡器的设计","authors":"Kusuma Neerugatti, Venugopal Pakala","doi":"10.1016/j.vlsi.2025.102487","DOIUrl":null,"url":null,"abstract":"<div><div>The paper presents a 2.54 GHz Active Inductor-based LC-Voltage Controlled Oscillator (AI-based LC-VCO) design. The AI is constructed based on a single-ended common-source NMOS/PMOS cascade model that generates negative transconductance in the gyrator model. The proposed design is a combination of AI, NMOS cross-coupled pair, and fixed tail current biasing together that optimizes the Q-point to maintain output swing, reduces power consumption and lowers phase noise at a wide tuning range. The findings demonstrate the active VCOs post-layout performance with phase noise of −117.61 dBc/1 MHz offset, power of 0.122 mW, FTR of 102.20 %, and occupies a layout area of 0.09177 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> with tape-out. Also, advanced simulations under Monte-Carlo and PVT analysis at Military standards (Temp. <span><math><mrow><mo>°</mo><mi>C</mi></mrow></math></span>: −55, 27, 85) are performed using the Cadence UMC-180 nm process at a supply of 1.8 V. Ultimately, it finds a high FoM of −141.15 dBc/Hz compared to current AI-based LC-VCOs. Therefore, the work is suitable for designing sub-6 GHz Charge Pump-PLLs for modern 5G and 6G Bluetooth/WLAN applications.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102487"},"PeriodicalIF":2.5000,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of 2.54 GHz active inductor-based LC-voltage controlled oscillator for bluetooth/WLAN applications\",\"authors\":\"Kusuma Neerugatti, Venugopal Pakala\",\"doi\":\"10.1016/j.vlsi.2025.102487\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The paper presents a 2.54 GHz Active Inductor-based LC-Voltage Controlled Oscillator (AI-based LC-VCO) design. The AI is constructed based on a single-ended common-source NMOS/PMOS cascade model that generates negative transconductance in the gyrator model. The proposed design is a combination of AI, NMOS cross-coupled pair, and fixed tail current biasing together that optimizes the Q-point to maintain output swing, reduces power consumption and lowers phase noise at a wide tuning range. The findings demonstrate the active VCOs post-layout performance with phase noise of −117.61 dBc/1 MHz offset, power of 0.122 mW, FTR of 102.20 %, and occupies a layout area of 0.09177 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> with tape-out. Also, advanced simulations under Monte-Carlo and PVT analysis at Military standards (Temp. <span><math><mrow><mo>°</mo><mi>C</mi></mrow></math></span>: −55, 27, 85) are performed using the Cadence UMC-180 nm process at a supply of 1.8 V. Ultimately, it finds a high FoM of −141.15 dBc/Hz compared to current AI-based LC-VCOs. Therefore, the work is suitable for designing sub-6 GHz Charge Pump-PLLs for modern 5G and 6G Bluetooth/WLAN applications.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102487\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-07-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001440\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001440","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Design of 2.54 GHz active inductor-based LC-voltage controlled oscillator for bluetooth/WLAN applications
The paper presents a 2.54 GHz Active Inductor-based LC-Voltage Controlled Oscillator (AI-based LC-VCO) design. The AI is constructed based on a single-ended common-source NMOS/PMOS cascade model that generates negative transconductance in the gyrator model. The proposed design is a combination of AI, NMOS cross-coupled pair, and fixed tail current biasing together that optimizes the Q-point to maintain output swing, reduces power consumption and lowers phase noise at a wide tuning range. The findings demonstrate the active VCOs post-layout performance with phase noise of −117.61 dBc/1 MHz offset, power of 0.122 mW, FTR of 102.20 %, and occupies a layout area of 0.09177 with tape-out. Also, advanced simulations under Monte-Carlo and PVT analysis at Military standards (Temp. : −55, 27, 85) are performed using the Cadence UMC-180 nm process at a supply of 1.8 V. Ultimately, it finds a high FoM of −141.15 dBc/Hz compared to current AI-based LC-VCOs. Therefore, the work is suitable for designing sub-6 GHz Charge Pump-PLLs for modern 5G and 6G Bluetooth/WLAN applications.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.