A fast transient response capless low-dropout regulator with NMOS-FVF structure

IF 2.5 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-08-05 DOI:10.1016/j.vlsi.2025.102481

Jiahao Xiong, Xiao Zhao, Bojiang Zhang, Yicheng Peng

引用次数: 0

Abstract

This paper presents an NMOS-FVF low-dropout regulator (LDO) with adaptive biasing. Leveraging the small gate capacitance and adaptive biasing mechanism, the proposed LDO achieves minimal undershoot and overshoot, along with an exceptionally short recovery time. Additionally, strategic incorporation of adaptive biasing substantially enhances load regulation, effectively addressing the limitations of inadequate load regulation commonly observed in traditional FVF-LDOs. The proposed design was fabricated in a 180 nm CMOS process, featuring a quiescent current of 110

μ

A and a maximum load current of 50 mA. Transient simulation results demonstrate an undershoot of 64 mV, an overshoot of 42 mV, and a recovery time of 30 ns.

查看原文本刊更多论文

基于NMOS-FVF结构的快速瞬态响应无帽低差调节器

提出了一种具有自适应偏置的NMOS-FVF低差稳压器（LDO）。利用小栅极电容和自适应偏置机制，所提出的LDO实现了最小的欠调和超调，以及极短的恢复时间。此外，自适应偏置的策略结合大大增强了负载调节，有效地解决了传统fvf - ldo中普遍存在的负载调节不足的局限性。该电路采用180 nm CMOS工艺，静态电流为110 μA，最大负载电流为50 mA。瞬态仿真结果表明，欠调值为64 mV，超调值为42 mV，恢复时间为30 ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.